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21 REMOTE CONTROLLER (REMC)
0x5347: REMC Interrupt Flag Register (REMC_IFLG)
Register name Address
Bit
REMC Interrupt
0x5347
D7–3 –
Flag Register
(8 bits)
D2
(REMC_IFLG)
D1
D0
This register indicates whether causes of data length counter underflow, input signal rising edge, and input signal
falling edge interrupts have occurred or not. When a REMC interrupt occurs, read the interrupt flags in this register
to determine the cause of interrupt that has occurred.
The interrupt flags are set to 1 when the data length counter underflows, a rising edge of the input signal is detected
or a falling edge of the input signal is detected if the corresponding interrupt enable bit has been set to 1. At the
same time, the REMC interrupt request signal is output to the ITC. The interrupt request signal sets the REMC
interrupt flag in the ITC to 1 and an interrupt occurs if other interrupt conditions meet the ITC and S1C17 Core
settings.
Note: To avoid occurrence of unnecessary interrupts, be sure to reset the interrupt flag before the
REMC interrupt is enabled using the interrupt enable bit.
D[7:3]
Reserved
D2
REMFIF: Falling Edge Interrupt Flag
This is the interrupt flag to indicate the falling edge interrupt cause occurrence status.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Has no effect
REMFIF is set to 1 at the falling edge of the input signal only when REMFIE (D2/REMC_IMSK
register) is set to 1.
D1
REMRIF: Rising Edge Interrupt Flag
This is the interrupt flag to indicate the rising edge interrupt cause occurrence status.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Has no effect
REMRIF is set to 1 at the rising edge of the input signal only when REMRIE (D1/REMC_IMSK
register) is set to 1.
D0
REMUIF: Underflow Interrupt Flag
This is the interrupt flag to indicate the underflow interrupt cause occurrence status.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Has no effect
REMUIF is set to 1 when the data length counter underflows only when REMUIE (D0/REMC_IMSK
register) is set to 1.
21-18
Name
Function
reserved
REMFIF
Falling edge interrupt flag
REMRIF
Rising edge interrupt flag
REMUIF
Underflow interrupt flag
Setting
–
1 Cause of
0 Cause of
interrupt
occurred
EPSON
Init. R/W
Remarks
–
–
0 when being read.
0
R/W Reset by writing 1.
interrupt not
0
R/W
occurred
0
R/W
S1C17704 TECHNICAL MANUAL
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