Data Transmit/Receive Control - Epson S1C17704 Technical Manual

18.5 Data Transmit/Receive Control

Before starting data transfer, set up the conditions as shown below.
(1) Select an input clock. See Section 18.3.
Set up the 8-bit timer to output the transfer clock if the internal clock is used as the transfer clock. See Chapter 12.
(2) Configure the transfer data format. See Section 18.4.
(3) Set IrDA mode when using the IrDA interface. See Section 18.8.
(4) Set up the interrupt conditions if the UART interrupt is used. See Section 18.7.
Note: Make sure that the UART is disabled (RXEN/UART_CTL register = 0) when setting the conditions
above.
∗ RXEN: UART Enable Bit in the UART Control (UART_CTL) Register (D0/0x4104)
Enabling data transmission/reception
First, set the RXEN bit (D0/UART_CTL register) to 1 to enable data transmission/reception. This puts the
transmitter/receiver in ready-to-transmit/receive status.
Note: Do not set the RXEN bit to 0 while the UART is transmitting/receiving data.
Data transmit control
To start transmission, write transmit data to the UART_TXD register (0x4101).
∗ UART_TXD: UART Transmit Data Register (0x4101)
Data is written to the transmit data buffer and the transmitter starts data transmission.
The buffered data is sent to the shift register for transmission and a start bit is output from the SOUT pin. Then
data in the shift register is output from the LSB. The transmit data bits are shifted in sync with the rising edge
of the sampling clock and output from the SOUT pin sequentially. After the MSB has been output, a parity bit (if
parity is enabled) and a stop bit are output.
The transmitter provides two status flags, TDBE (D0/UART_ST register) and TRBS (D2/UART_ST register).
∗ TDBE: Transmit Data Buffer Empty Flag in the UART Status (UART_ST) Register (D0/0x4100)
∗ TRBS: Transmit Busy Flag in the UART Status (UART_ST) Register (D2/0x4100)
The TDBE flag indicates the transmit data buffer status; it goes 0 when the application program writes data to
the transmit data buffer and returns to 1 when the data in the transmit data buffer is sent to the shift register for
transmitting. An interrupt can be generated when this flag goes 1 (see Section 18.7). Use this interrupt or read
the TDBE flag to check that the transmit data buffer is empty before transmitting the next data. Although the
transmit data buffer size is one byte, transmit data can be written while the previous data is being transmitted
as the shift register is separately provided. However, make sure that the transmit data buffer is empty before
writing transmit data. If data is written when the TDBE flag is 0, the previous transmit data in the transmit data
buffer is overwritten with the new data.
The TRBS flag indicates the shift register status; it goes 1 when transmit data is loaded from the transmit data
buffer and returns to 0 upon completion of a data transmission. Read this flag to check whether the transmitter
is busy or idle.
Sampling clock
SOUT
TDBE
TRBS
Interrupt
S1C17704 TECHNICAL MANUAL
S1 D0 D1 D2 D3 D4 D5 D6 D7 P S2 S1 D0 D1
Wr Wr
S1: Start bit, S2: Stop bit, P: Parity bit, Wr: Data write to transmit data buffer
Figure 18.5.1 Data Transmit Timing Chart
D7 P S2 S1 D0 D1
Wr
EPSON
18 UART
D7 P S2
18-5