Epson S1C17704 Technical Manual page 180

13 PWM & CAPTURE TIMER (T16E)
Setting fine mode for clock output
By default (after an initial reset), the clock output signal changes at the rising edge of the input clock when
compare data A becomes equal to the counter value.
In fine mode, the output signal changes according to bit 0 of compare data A (T16ECA0) when the
T16ECA0[15:1] value in the compare data A register becomes equal to the T16ETC[14:0] counter value.
When T16ECA0 is 0, the output signal changes at the rising edge of the input clock.
When T16ECA0 is 1, the output signal changes at the falling edge of the input clock a half cycle from the de-
fault setting.
Input clock
Counter value
T16E_CA
T16E_CB
Compare A signal
Compare B signal
TOUT output (INVOUT = 0)
TOUT output (INVOUT = 1)
As shown in the figure above, in fine mode the output clock duty ratio can be adjusted in the half cycle of the
input clock. However, when compare data A is 0, the timer outputs a pulse with a 1-cycle width as the input
clock, the same as the default setting.
In fine mode, the maximum value of compare data B is 2
can be set is 0 to (2 × compare data B - 1).
The fine mode is set using SELFM (D6/T16E_CTL register).
∗ SELFM: Fine Mode Select Bit in the PWM Timer Control (T16E_CTL) Register (D6/0x5306)
When 1 is written to SELFM, fine mode is set. At initial reset, the fine mode is disabled.
Precautions
(1) When using the output clock, set compare data as A ≥ 0 and B ≥ 1. The minimum settings are A = 0 and B = 1.
In this case, the timer output clock cycle is the input clock × 1/2.
(2) When compare data are set as A > B (or set as A > B × 2 in fine mode), the compare B match signal will be
generated but no compare A match signal will be generated. In this case, the timer output signal is fixed at
the low (or high when INVOUT = 1).
13-8
0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3
2 3
Figure 13.6.3 Clock Output in Fine Mode
EPSON
4
5
15
- 1 = 32,767 and the range of compare data A that
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