Epson S1C17704 Technical Manual page 288

2
20 I C
When STP is set to 1, the I
generate a STOP condition on the I
2
Furthermore, the I C module allows presetting for generating a STOP condition in advance. To do this, set STP
to 1 after checking if the I
upon completion of data transmission/reception (including an ACK transfer).
STP is automatically reset to 0 after a STOP condition has been generated.
2
The I C module does not support repeated START condition. A STOP condition cannot be omitted before
generating a new START condition for starting the next data transfer.
Wait state by setting TXE, RXE, STRT, and STP
If TXE (D9/I2C_DAT register), RXE (D10/I2C_DAT register), STRT (D0/I2C_CTL register), and STP (D1/
I2C_CTL register) have all been set to 0 when byte data and ACK transfer have finished, the I
the SCL output at low and enters wait state. The wait state will be canceled by writing 1 to TXE or RXE to
resume data transmission/reception or by writing 1 to STP to generate a STOP condition.
Disabling data transmission/reception
After data transfer (both transmission and reception) has finished, write 0 to the I2CEN bit to disable data
transmission/reception.
Always make sure that the RBUSY and TBUSY flags are 0 before data transmission/reception is disabled.
The data being transferred cannot be guaranteed if I2CEN is set to 0 during transmitting/receiving.
Timing charts
START
Start communication
condition
Register settings
PCLK
T16 Ch.2 output
SCL (input)
SCL (output)
SDA (input)
SDA (output)
STRT
STP
TXE
RXE
TBUSY
RBUSY
RBRDY
RTACK
Shift register
RTDT[7:0]
Interrupt
Figure 20.5.5 I
20-8
2
C module pulls up the SDA line from low to high with the SCL line held at high to
2
C bus. This makes the I
2
C is operating (TBUSY = 1 or RBUSY = 1). A STOP condition will be generated
Start transmission
Slave address transmission
A6 A5 A4 A3
valid shift shift shift
A[6:0] + DIR
C Timing Chart 1 (START condition → data transmission)
2
2
C bus in free status.
Set transmit data and TXE
A2 A1 A0
shift shift shift
EPSON
2
C module fixes
ACK reception Start transmission
Data transmission
ACK
DIR = 0 D7 D6
(ACK received)
shift valid shift
D[7:0]
S1C17704 TECHNICAL MANUAL