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6 INTERRUPT CONTROLLER (ITC)
D[7:0]
EIFT[7:0]: Interrupt Flags (for Level Trigger)
These bits are interrupt flags to indicate the interrupt cause occurrence status.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Has no effect
0 (W):
Has no effect
See the description for IIFT[7:0].
However, these interrupts must be set to level trigger mode using the ITC_ELVx register (0x4306 to
0x430c). Therefore, EIFTx cannot be reset by writing 1. To reset the EIFTx, write 1 to the interrupt flag
in the peripheral module.
Interrupt flag
EIFT0 (D0)
EIFT1 (D1)
EIFT2 (D2)
EIFT3 (D3)
EIFT4 (D4)
EIFT5 (D5)
EIFT6 (D6)
EIFT7 (D7)
Note: Even when a maskable interrupt request is accepted by the S1C17 Core and control branches off
to the interrupt handler routine, the interrupt flag is not reset. Consequently, if control is returned
from the interrupt handler routine by the reti instruction without resetting the interrupt flag in
a program, the same cause of interrupt occurs again. The interrupt flag of the level triggered
interrupt must be reset using the control register in the peripheral module.
6-14
Table 6.7.3 Causes of Hardware Interrupt and Interrupt Flags
P0 port interrupt: P00–P07 port inputs
P1 port interrupt: P10–P17 port inputs
Stopwatch timer interrupt: 100 Hz/10 Hz/1 Hz signal
Clock timer interrupt: 32 Hz/8 Hz/2 Hz/1 Hz signal
8-bit OSC1 timer interrupt: compare match
SVD interrupt: low supply voltage detection
LCD interrupt: frame signal
PWM & capture timer interrupt: compare A/compare B match
EPSON
Cause of hardware interrupt
S1C17704 TECHNICAL MANUAL
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