Clock Timer Interrupt - Epson S1C17704 Technical Manual

Cmos 16-bit single chip microcomputer
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15.5 Clock Timer Interrupt

The CT module can generate the following four types of interrupts:
• 32 Hz interrupt
• 8 Hz interrupt
• 2 Hz interrupt
• 1 Hz interrupt
The CT module has one interrupt signal to be output to the interrupt controller (ITC) and it is shared with the four
causes of interrupt. To determine the cause of interrupt that has occurred, read the interrupt flags in the CT module.
32 Hz, 8 Hz, 2 Hz, and 1 Hz interrupts
An interrupt request occurs at the falling edge of the 32 Hz, 8 Hz, 2 Hz, and 1 Hz signals, and it sets the
interrupt flag in the CT module to 1.
∗ CTIF32: 32 Hz Interrupt Flag in the Clock Timer Interrupt Flag (CT_IFLG) Register (D3/0x5003)
∗ CTIF8:
8 Hz Interrupt Flag in the Clock Timer Interrupt Flag (CT_IFLG) Register (D2/0x5003)
∗ CTIF2:
2 Hz Interrupt Flag in the Clock Timer Interrupt Flag (CT_IFLG) Register (D1/0x5003)
∗ CTIF1:
1 Hz Interrupt Flag in the Clock Timer Interrupt Flag (CT_IFLG) Register (D0/0x5003)
Set the interrupt enable bit corresponding to the interrupt flag to 1 when using the interrupt. If the interrupt
enable bit is set to 0 (default), the interrupt flag will not be set to 1 and an interrupt request by the corresponding
signal will not be sent to the ITC.
∗ CTIE32: 32 Hz Interrupt Enable Bit in the Clock Timer Interrupt Mask (CT_IMSK) Register (D3/0x5002)
∗ CTIE8:
8 Hz Interrupt Enable Bit in the Clock Timer Interrupt Mask (CT_IMSK) Register (D2/0x5002)
∗ CTIE2:
2 Hz Interrupt Enable Bit in the Clock Timer Interrupt Mask (CT_IMSK) Register (D1/0x5002)
∗ CTIE1:
1 Hz Interrupt Enable Bit in the Clock Timer Interrupt Mask (CT_IMSK) Register (D0/0x5002)
If CTIF∗ is set to 1, the CT module outputs the interrupt request signal to the ITC. The interrupt request signal
sets the clock timer interrupt flag in the ITC to 1 and an interrupt occurs if other interrupt conditions meet the
ITC and S1C17 Core settings.
The clock timer interrupt handler routine should read the CTIF* flags to check the signal that causes occurrence
of the interrupt.
Furthermore, the interrupt handler routine must reset (write 1 to) CTIF∗ in the CT module, not the clock timer
interrupt flag in the ITC, to clear the cause of interrupt.
Note: To avoid occurrence of unnecessary interrupts, be sure to reset the CTIF∗ flags before the clock
timer interrupt is enabled using CTIE∗.
ITC registers for clock timer interrupt
The clock timer asserts the interrupt signal sent to the ITC at the falling edge of the signal whose interrupt is
enabled according to the interrupt condition settings shown above. To generate a clock timer interrupt, set the
interrupt level and enable the interrupt using the ITC registers.
The following shows the control bits for the clock timer interrupt in the ITC.
Interrupt flag in the ITC
∗ EIFT3: Clock Timer Interrupt Flag in the Interrupt Flag (ITC_IFLG) Register (D3/0x4300)
Interrupt enable bit in the ITC
∗ EIEN3: Clock Timer Interrupt Enable Bit in the Interrupt Enable (ITC_EN) Register (D3/0x4302)
Interrupt level setup bits in the ITC
∗ EILV3[2:0]: CT Interrupt Level Bits in the External Interrupt Level Setup (ITC_ELV1) Register 1
(D[10:8]/0x4308)
Interrupt trigger mode select bit in the ITC (fixed at 1)
∗ EITG3: CT Interrupt Trigger Mode Select Bit in the External Interrupt Level Setup (ITC_ELV1) Register 1
(D12/0x4308)
S1C17704 TECHNICAL MANUAL
EPSON
15 CLOCK TIMER (CT)
15-5

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