Bcd Counters - Epson S1C17704 Technical Manual

Cmos 16-bit single chip microcomputer
Table of Contents

Advertisement

16 STOPWATCH TIMER (SWT)

16.2 BCD Counters

The stopwatch timer consists of two 4-bit BCD counters for counting 1/100 seconds and 1/10 seconds.
The count values can be read from the SWT_BCNT register.
1/100-second counter
∗ BCD100[3:0]: 1/100 Sec. BCD Counter Value in the Stopwatch Timer BCD Counter (SWT_BCNT) Register
(D[3:0]/0x5021)
1/10-second counter
∗ BCD10[3:0]: 1/10 Sec. BCD Counter Value in the Stopwatch Timer BCD Counter (SWT_BCNT) Register
(D[7:4]/0x5021)
Count-up pattern
To generate 100 Hz, 10 Hz, and 1 Hz signals from the 256 Hz source clock, the stopwatch timer changes the
count-up pattern for the counter as shown in Figure 16.2.1 using the feedback divider.
256 Hz
3
256
Approximate 100 Hz
(Feedback divider output)
0
1/100-second counter
Approximate 10 Hz
(1/100-second counter output)
26
256
Approximate 10 Hz
(1/100-second counter output)
0
1/10-second counter
1 Hz
(1/10-second counter output)
The feedback divider generates an approximate 100 Hz signal with 2/256-second and 3/256-second clock
cycles from the 256 Hz signal supplied from the OSC module.
The 1/100-second counter counts the approximate 100 Hz signal output by the feedback divider and generates
an approximate 10 Hz signal with 25/256-second and 26/256-second clock cycles.
The counter counts up in 2/256-second and 3/256-second intervals, therefore the count cycle is an approximate
1/100 seconds.
The 1/10-second counter counts the approximate 10 Hz signal output by the 1/100-second counter in 4:6 ratios
to generate a 1 Hz signal.
The counter counts up in 25/256-second and 26/256-second intervals, therefore the count cycle is an
approximate 1/10 seconds.
16-2
1/100-second counter count-up pattern 1
2
3
2
3
2
3
256
256
256
256
256
256
1
2
3
4
5
6
25
s
256
26
25
25
s
s
s
256
256
256
1
2
Figure 16.2.1 Count-up Pattern of Stopwatch Timer
1/100-second counter count-up pattern 2
2
3
2
3
3
256
256
256
256
256
7
8
9
0
1
1/10-second counter count-up pattern
26
26
s
s
s
256
256
3
4
5
26
× 6 + 25
× 4 = 1 s
256
256
EPSON
3
2
3
2
3
2
256
256
256
256
256
256
2
3
4
5
6
7
26
s
256
25
25
26
s
s
s
256
256
256
6
7
8
S1C17704 TECHNICAL MANUAL
3
2
256
256
8
9
26
s
256
9

Advertisement

Table of Contents
loading

Table of Contents