Receive Errors - Epson S1C17704 Technical Manual

18 UART

18.6 Receive Errors

Three types of receive errors can be detected in data reception.
The receive errors are causes of interrupt, so the error can be processed in the interrupt handler routine. Refer to
Section 18.7 for controlling the UART interrupts.
Parity error
If the PREN bit (D3/UART_MOD register) is set to 1 (parity enabled), the parity bit is checked when data is
received.
This parity check is performed when the data received in the shift register is loaded to the receive data buffer in
order to check conformity with the PMD bit (D2/UART_MOD register) setting (odd or even parity).
If any nonconformity is found in this check, a parity error is assumed and the parity error flag PER (D5/
UART_ST register) is set to 1.
Even when this error occurs, the received data in error is loaded to the receive data buffer and the receive
operation is continued. However, the received data in which a parity error has occurred cannot be guaranteed.
The PER flag (D5/UART_ST register) is reset to 0 by writing 1.
∗ PREN: Parity Enable Bit in the UART Mode (UART_MOD) Register (D3/0x4103)
∗ PMD: Parity Mode Select Bit in the UART Mode (UART_MOD) Register (D2/0x4103)
∗ PER: Parity Error Flag in the UART Status (UART_ST) Register (D5/0x4100)
Framing error
If data with a stop bit = 0 is received, the UART assumes that the data is out of sync and generates a framing
error.
If two stop bits are used, only the first stop bit is checked.
When this error occurs, the framing-error flag FER (D6/UART_ST register) is set to 1.
Even when this error occurs, the received data in error is loaded to the receive data buffer and the receive
operation is continued. However, the received data in which a framing error has occurred cannot be guaranteed,
even if no framing error is found in the following data received.
The FER flag (D6/UART_ST register) is reset to 0 by writing 1.
∗ FER: Framing Error Flag in the UART Status (UART_ST) Register (D6/0x4100)
Overrun error
Even when the receive data buffer is full (two data have been received), the next (third) data can be received
into the shift register. If there is no space in the buffer (data has not been read) when the third data has been
received, the third data in the shift register cannot be transferred to the buffer. If one more (fourth) data is
transferred to this UART, the shift register (third data) is overwritten with the fourth data and an overrun error
occurs.
When an overrun error occurs, the overrun error flag OER (D4/UART_ST register) is set to 1.
Even when this error occurs, the receive operation is continued.
The OER flag (D4/UART_ST register) is reset to 0 by writing 1.
∗ OER: Overrun Error Flag in the UART Status (UART_ST) Register (D4/0x4100)
18-8
EPSON
S1C17704 TECHNICAL MANUAL