0X4206: 8-Bit Timer Control Register (T8F_Ctl) - Epson S1C17704 Technical Manual

12 8-BIT TIMER (T8F)

0x4206: 8-bit Timer Control Register (T8F_CTL)

Register name Address Bit
8-bit Timer 0x4206 D15–12 –
Control Register (16 bits)
D11–8 TFMD[3:0]
(T8F_CTL)
D7–5 –
D4
D3–2 –
D1
D0
D[15:12] Reserved
D[11:8] TFMD[3:0]: Fine Mode Setup Bits
Corrects transfer rate error. (Default: 0x0)
The TFMD[3:0] bits specify a pattern of delays to be inserted in a 16-underflow period. The output
clock period will be prolonged for one count clock period per one delay inserted.
TFMD[3:0]
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0xc
0xd
0xe
0xf
Underflow signal (not corrected)
Underflow signal (corrected)
Output clock (not corrected)
Output clock (corrected)
D[7:5] Reserved
12-14
Name Function
reserved
Fine mode setup
reserved
TRMD Count mode select
reserved
PRESER
Timer reset
PRUN Timer run/stop control
Table 12.10.3 Delay Patterns Specified with TFMD[3:0]
1 2 3 4 5
– – – – –
– – – – –
– – – – –
– – – – –
– – – D –
– – – D –
– – – D –
– – – D –
– D – D –
– D – D –
– D – D –
– D – D –
– D D D –
– D D D –
– D D D D
– D D D D
Count clock
15
15
Figure 12.10.1 Delay Cycle Inserted in Fine Mode
Setting
–
0x0 to 0xf
–
1 One shot 0 Repeat
–
1 Reset 0 Ignored
1 Run 0 Stop
Underflow number
6 7 8 9 10
– – – – –
– – – – –
– – D – –
– – D – –
– – D – –
– – D – –
D – D – –
D – D – D
D – D – D
D – D – D
D D D – D
D D D – D
D D D – D
D D D – D
D D D – D
D D D D D
16
16
EPSON
Init. R/W Remarks
– – 0 when being read.
0x0 R/W Set a number of times
to insert delay into a
16-underflow period.
– – 0 when being read.
0 R/W
– – 0 when being read.
0 W
0 R/W
11 12 13 14
– – – –
– – – –
– – – –
– D – –
– D – –
– D – D
– D – D
– D – D
– D – D
– D – D
– D – D
D D – D
D D – D
D D D D
D D D D
D D D D
D: Indicates that a delay is inserted.
1
Delayed
S1C17704 TECHNICAL MANUAL
15 16
– –
– D
– D
– D
– D
– D
– D
– D
– D
D D
D D
D D
D D
D D
D D
D D
1