Chattering Filter For P0 Ports - Epson S1C17704 Technical Manual

10 I/O PORTS (P)

10.6 Chattering Filter for P0 Ports

The P0[3:0] and P0[7:4] ports are equipped with a chattering filter and allow selection whether the filter is used
or not. Furthermore, an input level check time can be selected when the filter is used. Use P0CFx[2:0] (P0_CHAT
register) provided for the P0[3:0] port and P0[7:4] port individually to set the filtering conditions.
∗ P0CF1[2:0]: P0[3:0] Chattering Filter Time Select Bits in the P0 Port Chattering Filter Control (P0_CHAT)
Register (D[2:0]/0x5208)
∗ P0CF2[2:0]: P0[7:4] Chattering Filter Time Select Bits in the P0 Port Chattering Filter Control (P0_CHAT)
Register (D[6:4]/0x5208)
Notes: • The check time to eliminate chattering means the maximum pulse width that can be
eliminated. The valid interrupt input needs a pulse width of the set check time (minimum) to
twice that of the check time (maximum).
• Input interrupts cannot be accepted in SLEEP mode if the CPU enters SLEEP mode when the
chattering filter is active. The chattering filter should be disabled (off) before executing the slp
instruction.
• Be sure to disable the P0 port interrupt before changing the P0_CHAT register (0x5208).
Unnecessary interrupt may occur if the register is changed when the P0 port interrupt has
been enabled.
• The internal signal may oscillate if the rise/fall time of the input signal is too long because the
input signal level transition to the threshold level duration of time is too long. This causes the
input interrupt to malfunction, therefore setup the input signal so that the rise/fall time is 25 ns
or less.
10-6
Table 10.6.1 Setting Input Level Check Time
P0CFx[2:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
(Default: 0x0, ∗ when OSC3 = 2 MHz, PCLK = OSC3)
EPSON
Check time *
16384/f (8 ms)
PCLK
8192/f (4 ms)
PCLK
4096/f (2 ms)
PCLK
2048/f (1 ms)
PCLK
1024/f (512 µs)
PCLK
512/f (256 µs)
PCLK
256/f (128 µs)
PCLK
Disabled (Off)
S1C17704 TECHNICAL MANUAL