Epson S1C17704 Technical Manual page 27

Classification
Shift and swap sr
sa
sl
swap
Immediate extension ext
Conversion cv.ab
cv.as
cv.al
cv.la
cv.ls
Branch jpr
jpr.d
jpa
ipa.d
jrgt
jrgt.d
jrge
jrge.d
jrlt
jrlt.d
jrle
jrle.d
jrugt
jrugt.d
jruge
jruge.d
jrult
jrult.d
jrule
jrule.d
jreq
jreq.d
jrne
jrne.d
call
call.d
calla
calla.d
ret
ret.d
int
intl
reti
reti.d
brk
retd
System control nop
halt
slp
ei
di
∗1 The ld.a instruction accesses memories in 32-bit length. During data transfer from a register to a memory, the
32-bit data in which the eight high-order bits are set to 0 is written to the memory. During reading from a memory,
the eight high-order bits of the read data are ignored.
∗2 The S1C17704 does not include a coprocessor. Therefore, the coprocessor instructions are not available.
S1C17704 TECHNICAL MANUAL
Mnemonic
%rd,%rs Logical shift to the right with the number of bits specifi ed by the register
%rd,imm7 Logical shift to the right with the number of bits specifi ed by immediate
%rd,%rs Arithmetic shift to the right with the number of bits specifi ed by the register
%rd,imm7 Arithmetic shift to the right with the number of bits specifi ed by immediate
%rd,%rs Logical shift to the left with the number of bits specifi ed by the register
%rd,imm7 Logical shift to the left with the number of bits specifi ed by immediate
%rd,%rs Bytewise swap on byte boundary in 16 bits
imm13
Extend operand in the following instruction
%rd,%rs Convert signed 8-bit data into 24 bits
%rd,%rs Convert signed 16-bit data into 24 bits
%rd,%rs Convert 32-bit data into 24 bits
%rd,%rs Converts 24-bit data into 32 bits
%rd,%rs Converts 16-bit data into 32 bits
sign10 PC relative jump
%rb
Delayed branching possible
imm7 Absolute jump
%rb
Delayed branching possible
sign7 PC relative conditional jump
Delayed branching possible
sign7 PC relative conditional jump
Delayed branching possible
sign7 PC relative conditional jump
Delayed branching possible
sign7 PC relative conditional jump
Delayed branching possible
sign7 PC relative conditional jump
Delayed branching possible
sign7 PC relative conditional jump
Delayed branching possible
sign7 PC relative conditional jump
Delayed branching possible
sign7 PC relative conditional jump
Delayed branching possible
sign7 PC relative conditional jump
Delayed branching possible
sign7 PC relative conditional jump
Delayed branching possible
sign10 PC relative subroutine call
%rb Delayed call possible
imm7 Absolute subroutine call
%rb Delayed call possible
Return from subroutine
Delayed return possible
imm5 Software interrupt
imm5,imm3 Software interrupt with interrupt level setting
Return from interrupt handling
Delayed call possible
Debug interrupt
Return from debug processing
No operation
HALT mode
SLEEP mode
Enable interrupts
Disable interrupts
Function
Branch condition: !Z & !(N ^ V)
Branch condition: !(N ^ V)
Branch condition: N ^ V
Branch condition: Z | N ^ V
Branch condition: !Z & !C
Branch condition: !C
Branch condition: C
Branch condition: Z | C
Branch condition: Z
Branch condition: !Z
EPSON
2 CPU
2-5