0X430E: Internal Interrupt Level Setup Register 0 (Itc_Ilv0) - Epson S1C17704 Technical Manual

0x430e: Internal Interrupt Level Setup Register 0 (ITC_ILV0)

Register name Address Bit
Internal 0x430e D15–11 –
Interrupt Level (16 bits)
D10–8 IILV1[2:0]
Setup Register 0
D7–3 –
(ITC_ILV0)
D2–0 IILV0[2:0]
D[15:11] Reserved
D[10:8] IILV1[2:0]: 16-bit Timer Ch.0 Interrupt Level Bits
Sets the interrupt level (0 to 7) of the 16-bit timer Ch.0 interrupt. (Default: 0)
If the level is set below the IL value of the PSR, the S1C17 Core does not accept the interrupt request.
In the ITC, the interrupt level is used when two or more causes of interrupt occur simultaneously.
If two or more causes of interrupt that have been enabled by the interrupt enable register occur
simultaneously, the cause of interrupt whose Interrupt Level Setup Register contains the highest value
is allowed by the ITC to send an interrupt request to the S1C17 Core.
If two or more causes of interrupt that have the same interrupt level occur, the interrupt with the
smallest vector number is processed first.
Other causes of interrupt are kept pending until all interrupts of higher priority are accepted by the
S1C17 Core.
If another cause of interrupt of higher priority occurs during outputting an interrupt request signal,
the ITC changes the vector number and interrupt level to those of the new cause of interrupt. The first
interrupt request is left pending.
D[7:3] Reserved
D[2:0] IILV0[2:0]: 8-bit Timer Interrupt Level Bits
Sets the interrupt level (0 to 7) of the 8-bit timer interrupt. (Default: 0)
See the description of IILV1[2:0] (D[10:8]).
S1C17704 TECHNICAL MANUAL
Name Function
reserved
T16 Ch.0 interrupt level
reserved
T8 interrupt level
EPSON
6 INTERRUPT CONTROLLER (ITC)
Setting Init. R/W
– – – 0 when being read.
0 to 7 0x0 R/W
– – – 0 when being read.
0 to 7 0x0 R/W
Remarks
6-21