I/O Map - Epson S1C17704 Technical Manual

3 MEMORY MAP, BUS CONTROL

3.5.3 I/O Map

This section shows the I/O map table for the internal peripheral area. For details of each control register, see the I/O
register list in Appendix or description for each peripheral module.
Peripheral Address
Prescaler 0x4020
(8-bit device)
0x4021–0x403f –
UART 0x4100
(with IrDA)
0x4101
(8-bit device)
0x4102
0x4103
0x4104
0x4105
0x4106–0x411f –
8-bit timer 0x4200
(with fine mode)
0x4202
(16-bit device)
0x4204
0x4206
0x4208–0x421f –
16-bit timer 0x4220
Ch. 0
0x4222
(16-bit device)
0x4224
0x4226
0x4228–0x423f –
16-bit timer 0x4240
Ch. 1
0x4242
(16-bit device)
0x4244
0x4246
0x4248–0x425f –
16-bit timer 0x4260
Ch. 2
0x4262
(16-bit device)
0x4264
0x4266
0x4268–0x427f –
Interrupt 0x4300
controller
0x4302
(16-bit device)
0x4304
0x4306
0x4308
0x430a
0x430c
0x430e
0x4310
0x4312
0x4314
0x4316–0x431f –
SPI 0x4320
(16-bit device)
0x4322
0x4324
0x4326
0x4328–0x433f –
2
I C 0x4340
(16-bit device)
0x4342
0x4344
0x4346
0x4348–0x435f –
3-8
Table 3.5.3.1 I/O Map (Internal Peripheral Area 1)
Register name
PSC_CTL Prescaler Control Register
–
UART_ST UART Status Register
UART_TXD UART Transmit Data Register
UART_RXD UART Receive Data Register
UART_MOD UART Mode Register
UART_CTL UART Control Register
UART_EXP UART Expansion Register
–
T8F_CLK 8-bit Timer Input Clock Select Register
T8F_TR 8-bit Timer Reload Data Register
T8F_TC 8-bit Timer Counter Data Register
T8F_CTL 8-bit Timer Control Register
–
T16_CLK0 16-bit Timer Ch.0 Input Clock Select Register
T16_TR0 16-bit Timer Ch.0 Reload Data Register
T16_TC0 16-bit Timer Ch.0 Counter Data Register
T16_CTL0 16-bit Timer Ch.0 Control Register
–
T16_CLK1 16-bit Timer Ch.1 Input Clock Select Register
T16_TR1 16-bit Timer Ch.1 Reload Data Register
T16_TC1 16-bit Timer Ch.1 Counter Data Register
T16_CTL1 16-bit Timer Ch.1 Control Register
–
T16_CLK2 16-bit Timer Ch.2 Input Clock Select Register
T16_TR2 16-bit Timer Ch.2 Reload Data Register
T16_TC2 16-bit Timer Ch.2 Counter Data Register
T16_CTL2 16-bit Timer Ch.2 Control Register
–
ITC_IFLG Interrupt Flag Register
ITC_EN Interrupt Enable Register
ITC_CTL ITC Control Register
ITC_ELV0 External Interrupt Level Setup Register 0
ITC_ELV1 External Interrupt Level Setup Register 1
ITC_ELV2 External Interrupt Level Setup Register 2
ITC_ELV3 External Interrupt Level Setup Register 3
ITC_ILV0 Internal Interrupt Level Setup Register 0
ITC_ILV1 Internal Interrupt Level Setup Register 1
ITC_ILV2 Internal Interrupt Level Setup Register 2
ITC_ILV3 Internal Interrupt Level Setup Register 3
–
SPI_ST SPI Status Register
SPI_TXD SPI Transmit Data Register
SPI_RXD SPI Receive Data Register
SPI_CTL SPI Control Register
–
2
I2C_EN I C Enable Register
I2C_CTL I 2 C Control Register
I2C_DAT I 2 C Data Register
I2C_ICTL I 2 C Interrupt Control Register
–
Starts/stops the prescaler.
Reserved
Indicates transfer, buffer and error statuses.
Transmit data
Receive data
Sets transfer data format.
Controls data transfer.
Sets IrDA mode.
Reserved
Selects a prescaler output clock.
Sets reload data.
Counter data
Sets the timer mode and starts/stops the timer.
Reserved
Selects a prescaler output clock.
Sets reload data.
Counter data
Sets the timer mode and starts/stops the timer.
Reserved
Selects a prescaler output clock.
Sets reload data.
Counter data
Sets the timer mode and starts/stops the timer.
Reserved
Selects a prescaler output clock.
Sets reload data.
Counter data
Sets the timer mode and starts/stops the timer.
Reserved
Indicates/resets interrupt occurrence status.
Enables/disables each maskable interrupt.
Enables/disables the ITC.
Sets the P0 and P1 interrupt levels and
trigger modes.
Sets the stopwatch timer and clock timer
interrupt levels and trigger modes.
Sets the 8-bit OSC1 timer and SVD interrupt
levels and trigger modes.
Sets the LCD and PWM & capture timer
interrupt levels and trigger modes.
Sets the 8-bit timer and 16-bit timer Ch. 0
interrupt levels.
Sets the 16-bit timer Ch. 1 and 16-bit timer
Ch. 2 interrupt levels.
Sets the UART and remote controller inter-
rupt levels.
Sets the SPI and I
Reserved
Indicates transfer and buffer statuses.
Transmit data
Receive data
Sets the SPI mode and enables data transfer.
Reserved
Enables the I
Controls the I
transfer status.
Transmit/receive data
Controls the I
Reserved
EPSON
Function
2
C interrupt levels.
2
C module.
2 C operation and indicates
2 C interrupt.
S1C17704 TECHNICAL MANUAL