Transfer Clock - Epson S1C17704 Technical Manual

18.3 Transfer Clock

The UART allows the application to select either the internal clock or an external clock as the transfer clock. Use
the SSCK bit (D0/UART_MOD register) for this selection.
∗ SSCK: Input Clock Select Bit in the UART Mode (UART_MOD) Register (D0/0x4103)
Note: Make sure that the UART is disabled (RXEN/UART_CTL register = 0) when alter the SSCK bit.
∗ RXEN: UART Enable Bit in the UART Control (UART_CTL) Register (D0/0x4104)
Internal clock
When SSCK is set to 0 (default), the internal clock is selected. The UART uses the 8-bit timer output clock as
the transfer clock. Therefore, it is necessary to program the 8-bit timer so that it will output a clock according to
the transfer rate.
See Chapter 12, "8-bit Timer (T8F)," for controlling the 8-bit timer.
External clock
When SSCK is set to 1, an external clock is selected. Configure the P25 pin as the SCLK pin (see Section 18.2)
and input an external clock to the pin.
Notes: • The UART divides the 8-bit timer output clock or external clock by 16 to generate the sampling
clock. Make sure of the division ratio when setting a transfer rate.
• The frequency of the external clock input from the SCLK pin must be half of PCLK or lower
and the clock duty ratio must be 50%.
S1C17704 TECHNICAL MANUAL
EPSON
18 UART
18-3