Memory Map, Bus Control - Epson S1C17704 Technical Manual

3 Memory Map, Bus Control

Figure 3.1 shows the S1C17704 memory map.
0xff ffff
Reserved for core I/O area
(1K bytes, 1 cycle)
0xff fc00
0xff fbff
0x08 0560
0x08 055f Display RAM area
(576 bytes, 2–5 cycles)
(Device size: 8 bits)
0x08 0000
0x07 ffff
0x01 8000
0x01 7fff
(64K bytes, 1–5 cycles)
(Device size: 16 bits)
0x00 8000
0x00 7fff
0x00 6000
0x00 5fff
Internal peripheral area 2
(4K bytes, 3 cycles)
0x00 5000
0x00 4fff
0x00 4400
0x00 43ff
Internal peripheral area 1
(1K bytes, 1 cycle)
0x00 4000
0x00 3fff
0x00 1000
0x00 0fff
Debug RAM area (64 bytes)
0x00 0fc0
Internal RAM area
(4K bytes, 1 cycle)
(Device size: 32 bits)
0x00 0000
S1C17704 TECHNICAL MANUAL
reserved
reserved
Flash area
Vector table
reserved
reserved
reserved
Figure 3.1 S1C17704 Memory Map
0x5360–0x5fff
0x5340–0x535f
0x5320–0x533f
0x5300–0x531f
0x52c0–0x52ff
0x52a0–0x52bf
0x5280–0x529f
0x5200–0x527f
0x5140–0x51ff
0x5120–0x513f
0x5100–0x511f
0x50e0–0x50ff
0x50c0–0x50df
0x50a0–0x50bf
0x5080–0x509f
0x5060–0x507f
0x5040–0x505f
0x5020–0x503f
0x5000–0x501f
0x4360–0x43ff
0x4340–0x435f
0x4320–0x433f
0x4300–0x431f
0x4280–0x42ff
0x4260–0x427f
0x4240–0x425f
0x4220–0x423f
0x4200–0x421f
0x4120–0x41ff
0x4100–0x411f
0x4040–0x40ff
0x4020–0x403f
0x4000–0x401f
EPSON
3 MEMORY MAP, BUS CONTROL
Peripheral function (Device size)
reserved –
Remote controller (8 bits)
MISC registers (8 bits)
PWM & capture timer (16 bits)
reserved –
Port MUX (8 bits)
reserved –
P ports (8 bits)
reserved –
Power controller (8 bits)
SVD circuit (8 bits)
reserved (8 bits)
8-bit OSC1 timer (8 bits)
LCD driver (8 bits)
Clock generator (8 bits)
Oscillator (8 bits)
Watchdog timer (8 bits)
Stopwatch timer (8 bits)
Clock timer (8 bits)
reserved (16 bits)
2
I C (16 bits)
SPI (16 bits)
Interrupt controller (16 bits)
reserved (16 bits)
16-bit timer Ch. 2 (16 bits)
16-bit timer Ch. 1 (16 bits)
16-bit timer Ch. 0 (16 bits)
8-bit timer (16 bits)
reserved (8 bits)
UART (8 bits)
reserved (8 bits)
Prescaler (8 bits)
reserved (8 bits)
3-1