Chip Select; Accessing Display Data Ram And Internal Register - Epson S1D15722 Series Technical Manual

6. FUNCTIONAL DESCRIPTION
When writing serial data
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CS
D7
D6
SI
SCL
1 2
A0
When reading serial data
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CS
SI
D7 D6
SCL
A0
* When the chip is inactive, the counter is reset to the initial state. Continuous serial clock input is possible,
however, it is recommended to clear the counter by setting
time of serial data input so that malfunction caused by external noise can be prevented. When reading serial
data, continuously read data by entering serial clock from the SCL pin with the setting left
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instead of setting CS = HIGH after the read command. After getting the read data, to set
necessary.
* For serial interface, read from display data RAM is not enabled.
* For SCL signal, great care should be taken for wiring termination reflection and external noise. It is
recommended to check operation using the actual equipment.

6.1.4 Chip Select

Since this IC has chip select pin, parallel interface or serial interface is enabled when
When the chip select is inactive, D0 to D7 are in the state of high impedance and input of A0,
and SCL is disabled. When serial interface is selected, shift register and counter are reset.

6.1.5 Accessing Display Data RAM and Internal Register

Since this IC is accessed as a kind of pipeline processing between LSIs via bus holder coming with internal
data bus, wait time is not necessary if the cycle time is satisfied, enabling high-speed data transmission.
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D5 D4 D3 D2
3 4 5 6
D5 D4 D3 D2 D1
Read status command
Fig.6.1 Signal Chart of Serial Interface
D7
D1 D0
7 8 1
D0 D7 D6
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CS = HIGH for every 8 bits of serial clock at the
EPSON S1D15722D01B000 Technical Manual (Rev.1.1)
D6 D5 D4 D3
D2
2 3 4 5 6
D5 D4 D3 D2
Output data
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CS = HIGH is
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CS = LOW is set.
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RD,
D1 D0
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CS = LOW
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WR, SI,