Samsung S5PC100 User Manual page 1633

AUDIO SUB-SYSTEM
2. Normal Mode
CPU writes decoded MP3 data to external DDR memory.
External DMA outside Audio sub-system transfers data from external DDR memory to I2S in case of I2S
request.
3. Enter to Deep IDLE Mode from Normal Mode
Wait for external DMA operation to complete.
After end of external DMA operation, programmers can know where the next data to be sent is.
Assert LPMP3_MODE_SEL bit in Clock Controller module. This operation changes mux interface in SRAM
wrapper (Refer to Figure 10.1-1). Now, SRAM wrapper switches rotation buffers in CAMIF to temporary
sound buffers.
CPU can transfer decoded MP3 data to SRAM wrapper in Audio sub-system.
If the proper size of MP3 decoded data is in SRAM wrapper, internal DMA in I2S is turned on to supply
decoded MP3 data from SRAM wrapper to I2S internal FIFO.
After CPU transfers all the decoded MP3 data to SRAM wrapper, S5PC100 enters to Deep IDLE mode.
4. Exit from Deep IDLE Mode
Using the pre-defined address based on interrupt condition like level interrupt or transfer-done interrupt,
external DMA is configured.
After external DMA is on, LPMP3_MODE_SEL bit should be low for I2S to communicate with external DMA.
This operation changed mux interface in SRAM wrapper. Now, SRAMs in SRAM wrapper are returned to
CAMIF.
10.1-4
S5PC100 USER'S MANUAL (REV1.0)