Samsung S5PC100 User Manual page 1616

S5PC100 USER'S MANUAL (REV1.0)
MFC (MULTI FORMAT CODEC)
9.6.8 INTERRUPT CONTROL
To a host processor
The FIMV-MFCV4.0 codec processor can generate an interrupt request to a host processor. Basically, this
interrupt is used to indicate completion of encoding or decoding of a frame. The interrupt signal, IREQ, is active
HIGH and is retained till the host processor clears it by writing '1' to interrupt clear register of the host interface.
As interrupt sources, there're 3 signals.
1. Frame done signal - means the end of frame's encoding/decoding.
2. DMA done signal - means the end of DMA's whole job in VSP during a job of loading initial F/W.
3. F/W done signal - means that F/W's job ends completely.
From a host processor
A host processor can control interrupt control using mask register.
9.11-48