Samsung S5PC100 User Manual page 1647

I2S CONTROLLER(5.1CH)
The Data is aligned in the RX FIFO for 24-bit/ channel BLC is shown in below figure.
31
INVALID
INVALID
INVALID
INVALID
The RXCHPAUSE in the I2SCON register stops the serial data reception on the I2SSDI. The reception is
stopped once the current Left/ Right channel is received.
If the control registers in the I2SCON Register (I2S Control Register) and I2SMOD Register (I2S Mode
Register) are to be reprogrammed then it is advisable to disable the RX channel.
Check the Status of RX FIFO by checking the bits in the I2SFIC Register (I2S FIFO Control Register).
10.2-14
23
Figure 10.2-9 RX FIF0 Structure for BLC = 10 (24-bit/channel)
BLC = 10 (24-bit/channel)
LEFT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
S5PC100 USER'S MANUAL (REV1.0)
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