Samsung S5PC100 User Manual page 1614

MFC (MULTI FORMAT CODEC)
9.5.5 FRAME NUMBER READING REGISTER (FRAME_NUM, R, ADDRESS = 0xf100_0410)
FRAME_NUM
FRAME_NUM
9.6 INTERRUPT CONTROL REGISTER
9.6.1 INTERRUPT CONTROL REGISTER (INT_OFF, R/W, ADDRESS = 0xf100_0500)
INT_OFF
Reserved
INT_OFF
9.6.2 INTERRUPT LEVEL SELECTION CONTROL REGISTER (INT_PULSE_SEL, R/W, ADDRESS =
0xf100_0504)
INT_PULSE_SEL
Reserved
INT_PULSE_SEL
9.6.3 INTERRUPT CLEAR REGISTER (INT_DONE_CLEAR, R/W, ADDRESS = 0xf100_0508)
INT_DONE_CLEAR
Reserved
INT_DONE_CLEAR
9.6.4 OPERATION STATUS REGISTER (OPERATION_DONE, R, ADDRESS = 0xf100_050c)
OPERATION_DONE
Reserved
OPERATION_DONE
9.11-46
Bit
Frame count value indicates to external host. Host can
[31:0]
check what frame is operated.
Bit
[31:1] Reserved
Interrupt control register. If Interrupt is disabled, then all done
signal checking is by polling mode.
[0]
0 = interrupt enable
1 = interrupt disable
Bit
[31:1] Reserved
0 = Level Interrupt
[0]
1 = Pulse Interrupt
Bit
[31:1] Reserved
[0] Interrupt clear when INT_MODE is 0 and INT_OFF is 0.
Bit
[31:1] Reserved
MFC done check signal, use polling mode.
[0] 0 = MFC encoder/decoder running.
1 = MFC encoder/decoder done.
S5PC100 USER'S MANUAL (REV1.0)
Description
Description
Description
Description
Description
Reset Value
0
Reset Value
0
0
Reset Value
0
0
Reset Value
0
0
Reset Value
0
0