Samsung S5PC100 User Manual page 1604

MFC (MULTI FORMAT CODEC)
9.2.4 FIRMWARE END REGISTER (FW_END, R/W, ADDRESS = 0xf100_010c)
FW_END
Reserved
FW_END
9.2.5 BUS MASTER SETTING REGISTER (BUS_MASTER, R/W, ADDRESS = 0xf100_0110)
BUS_MASTER
Reserved
BUS_MASTER
9.2.6 FRAME START REGISTER (FRAME_START, R/W, ADDRESS = 0xf100_0114)
FRAME_START
Reserved
FRAME_START
9.11-36
Bit
[31:1] Reserved
This signal means external host notifies encoding/decoding
operation about the end of all video processing jobs. IP
[0] terminates ARM7 processing after receiving this signal.
1 = Terminate F/W
0 = Normal operation
Bit
[31:1] Reserved
This register sets the master of DMA before the setting of DMA
in external host. If 1, external bus master is the host
0 = bus master is MFC. <ex. MFC can write DMA
[0]
register>
1 = bus master is Host. <ex. Host can write DMA
register>
Bit
[31:1] Reserved
This is a frame level start signal that IP, video codec,
encodes/decodes from external host. It is triggered when it's
[0] high.
Note: This bit is reset to 0 automatically when the FW reads
this bit.
S5PC100 USER'S MANUAL (REV1.0)
Description
Description
Description
Reset
Value
0
0
Reset
Value
0
0
Reset
Value
0
0