Samsung S5PC100 User Manual page 1641

I2S CONTROLLER(5.1CH)
6 PROGRAMMING GUIDE
The I2S bus interface is accessed either by the processor using programmed I/O instructions or by the DMA
controller.
6.1 INITIALIZATION
1. Before you use I2S bus interface, you must configure GPIOs to I2S mode and check signal's direction. The
I2SLRCLK, I2SSCLK and I2SCDCLK are inout-type. The each of I2SSDI and I2SSDO is input and output.
2. Select clock source. The S5PC100 has three clock sources namely PCLK, EPLL and external codec. For
more details refer to Figure 10.2-2 and Figure 10.2-3.
6.2 PLAY MODE (TX MODE) WITH DMA
1. TXFIFO is flushed before operation. If you do not distinguish Master/ Slave mode from TX/RX mode, you
must study Master/Slave mode and TX/RX mode. For more information refer to "Section 5.1 Master/ Slave".
2. To configure I2SMOD register and I2SPSR (I2S pre-scaler register) properly.
3. To operate system in stability, the internal TXFIFO should be almost full before transmission. Starts DMA to
fill TXFIFO.
4. Basically, I2S bus does not support the interrupt. Therefore, you check state by polling through accessing
SFR.
5. If TXFIFO is full, assert the I2SACTIVE.
6.3 RECORDING MODE (RX MODE) WITH DMA
1. RXFIFO is flushed before operation. If you do not distinguish between Master/ Slave mode and TX/RX mode,
you must study Master/ Slave mode and TX/RX mode. For more information refer to "Section 5.1
Master/Slave.
2. To configure I2SMOD register and I2SPSR (I2S pre-scaler register) properly.
3. To operate system in stability, the internal RXFIFO should have minimum one data before DMA operation.
Assert the I2SACTIVE.
4. Check RXFIFO state by polling through accessing SFR.
5. If RXFIFO is not empty, start RXDMACTIVE.
10.2-8
S5PC100 USER'S MANUAL (REV1.0)