Samsung S5PC100 User Manual page 1649

I2S CONTROLLER(5.1CH)
8 REGISTER DESCRIPTION
Register Address
I2SCON 0xF200_0000
I2SMOD 0xF200_0004
I2SFIC 0xF200_0008
I2SPSR 0xF200_000C
I2STXD 0xF200_0010
I2SRXD 0xF200_0014
I2SFICS 0xF200_0018
I2STXDS 0xF200_001C
I2SAHB 0xF200_0020
I2SSTR 0xF200_0024
I2SSIZE 0xF200_0028
I2STRNCNT 0xF200_002C
I2SLVL0ADDR 0xF200_0030
I2SLVL1ADDR 0xF200_0034
I2SLVL2ADDR 0xF200_0038
I2SLVL3ADDR 0xF200_003C
NOTE: All registers of I2S interface are accessible by word unit with STR/ LDR instructions.
8.1 I2S INTERFACE CONTROL REGISTER (I2SCON, R/W, ADDRESS = 0XF200_0000)
I2SCON
SW_RST
Reserved [30:27]
FRXOFSTATUS
10.2-16
Table 10.2-3 Register Summary of I2S Interface
R/W
R/W I2S Interface Control Register
R/W I2S Interface Mode Register
I2S Interface Primary Tx FIFO & Rx FIFO Control
R/W
Register
R/W I2S Interface Clock Divider Control Register
I2S Interface Transmit Primary Sound Data
W
Register
R I2S Interface Receive Data Register
I2S Interface Secondary TXFIFO_S Control
R/W
Register
W I2S Interface Secondary Transmit Data Register
R/W I2S AHB DMA Control Register
R/W I2S AHB DMA Start Address Register
R/W I2S AHB DMA Size Register
R I2S AHB DMA Transfer Count Register
R/W I2S AHA DMA Interrupt Level 0 Register
R/W I2S AHA DMA Interrupt Level 1 Register
R/W I2S AHA DMA Interrupt Level 2 Register
R/W I2S AHA DMA Interrupt Level 3 Register
Bit
[31] I2S s/w reset control. This should be set to 1 after I2S
clock is stable.
0 = Reset I2S module (default)
1 = Un-reset I2S module
Reserved
[26] RX FIFO Over Flow Interrupt Status. And this is used by
interrupt clear bit. When this is high, you can do interrupt
clear by writing '1'.
0 = Interrupt did not occurred.
1 = Interrupt occurred.
Description
Description
S5PC100 USER'S MANUAL (REV1.0)
Reset Value
0x8000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
R/W
R/W
R
R/W
0x000
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Reset
Value
0
0x0
0