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Manuals and User Guides for Intel Agilex Series. We have
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Intel Agilex Series manual available for free PDF download: Configuration User Manual
Intel Agilex Series Configuration User Manual (230 pages)
Brand:
Intel
| Category:
Computer Hardware
| Size: 3.41 MB
Table of Contents
Table of Contents
2
Intel ® Agilex ™ Configuration User Guide
6
Intel ® Agilex ™ Configuration Overview
6
Configuration and Related Signals
9
Intel Download Cables Supporting Configuration in Intel Agilex Devices
10
Intel Agilex Configuration Architecture
12
Secure Device Manager
14
Intel Agilex Configuration Details
18
Intel Agilex Configuration Timing Diagram
18
Configuration Flow Diagram
23
Device Response to Configuration and Reset Events
26
Additional Clock Requirements for HPS and Transceivers
26
Intel Agilex Configuration Pins
28
SDM Pin Mapping
28
MSEL Settings
29
Device Configuration Pins for Optional Configuration Signals
31
Configuration Clocks
48
Setting Configuration Clock Source
48
OSC_CLK_1 Clock Input
49
Intel Agilex Configuration Time Estimation
50
Generating Compressed .Sof File
51
Intel Agilex Configuration Schemes
53
Avalon-ST Configuration
53
Avalon-ST Configuration Scheme Hardware Components and File Types
55
Enabling Avalon-ST Device Configuration
57
The AVST_READY Signal
57
RBF Configuration File Format
60
Avalon-ST Single-Device Configuration
61
Debugging Guidelines for the Avalon-ST Configuration Scheme
64
IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
65
AS Configuration
102
AS Configuration Scheme Hardware Components and File Types
103
AS Single-Device Configuration
106
AS Using Multiple Serial Flash Devices
107
AS Configuration Timing Parameters
108
Maximum Allowable External AS_DATA Pin Skew Delay Guidelines
109
Programming Serial Flash Devices
110
Serial Flash Memory Layout
114
As_Clk
115
Active Serial Configuration Software Settings
116
Intel Quartus Prime Programming Steps
117
Debugging Guidelines for the as Configuration Scheme
123
JTAG Configuration
124
JTAG Configuration Scheme Hardware Components and File Types
126
JTAG Device Configuration
127
JTAG Multi-Device Configuration
130
Debugging Guidelines for the JTAG Configuration Scheme
132
Including the Reset Release Intel FPGA IP in Your Design
134
Understanding the Reset Release IP Requirement
135
Instantiating the Reset Release IP in Your Design
137
Gating the PLL Reset Signal
137
Guidance When Using Partial Reconfiguration (PR)
138
Detailed Description of Device Configuration
138
Device Initialization
140
Preventing Register Initialization During Power-On
140
Embedded Memory Block Initial Conditions
142
Protecting State Machine Logic
142
Remote System Update (RSU)
144
Remote System Update Functional Description
146
RSU Glossary
146
Remote System Update Using as Configuration
148
Remote System Update Configuration Images
149
Remote System Update Configuration Sequence
150
RSU Recovery from Corrupted Images
151
Updates with the Factory Update Image
154
Guidelines for Performing Remote System Update Functions for Non-HPS
155
Commands and Responses
156
Operation Commands
158
Error Code Responses
166
Error Code Recovery
167
Quad SPI Flash Layout
168
High Level Flash Layout
168
Detailed Quad SPI Flash Layout
175
Generating Remote System Update Image Files Using the Programming File Generator
182
Generating the Initial RSU Image
182
Generating an Application Image
187
Generating a Factory Update Image
189
Command Sequence to Perform Quad SPI Operations
194
Remote System Update from FPGA Core Example
194
Prerequisites
195
Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
196
Programming Flash Memory with the Initial Remote System Update Image
200
Reconfiguring the Device with an Application or Factory Image
201
Adding an Application Image
202
Removing an Application Image
205
Intel Agilex Configuration Features
207
Device Security
207
Configuration Via Protocol
207
Partial Reconfiguration
209
Intel Agilex Debugging Guide
210
Configuration Debugging Checklist
210
Intel Agilex Configuration Architecture Overview
212
Understanding Configuration Status Using Quartus_Pgm Command
212
Configuration File Format Differences
213
Understanding Seus
214
Reading the Unique 64-Bit CHIP ID
214
E-Tile Transceivers May Fail to Configure
214
Understanding and Troubleshooting Configuration Pin Behavior
215
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