Support For Small Form Factor Design Ddr Data Bus Routing; Control Signals - Scke[3:0], Scs#[3:0]; Table 26. Control Signal To So-Dimm Mapping - Intel 855PM Design Manual

System Memory Design Guidelines (DDR-SDRAM)
6.1.1.4.

Support for Small Form Factor Design DDR Data Bus Routing

The layout and routing guidelines for the system memory interface of the Intel 855PM MCH have been
optimized to address the requirements of small form factor designs (i.e., mini-note, sub-note, and tablet
PCs). The design guidelines allow the routing of SDQ[71:0] and SDQS[8:0] from the MCH pin to the
series resistor (Rs) to be as short as 0.5 inches.
6.1.2. Control Signals – SCKE[3:0], SCS#[3:0]
The Intel 855PM MCH control signals, SCKE[3:0] and SCS#[3:0], are common clocked signals. They
are "clocked" into the DDR-SDRAM devices using clock signals SCK/SCK#[5:0]. The MCH drives the
control and clock signals together, with the clocks crossing in the valid control window. The MCH
provides one chip select (CS) and one clock enable (CKE) signal per SO-DIMM physical device row.
Two chip select and two clock enable signals will be routed to each SO-DIMM. Refer to Table 26 for
the CKE and CS# signal to SO-DIMM mapping.

Table 26. Control Signal to SO-DIMM Mapping

Signal
SCS#[0]
SCS#[1]
SCS#[2]
SCS#[3]
SCKE[0]
SCKE[1]
SCKE[2]
SCKE[3]
The control signal group routing starting from MCH is as follows. The control signal routing should
transition immediately from an external layer to an internal signal layer under the MCH. Keep to the
same internal layer until transitioning back to an external layer and connect to the appropriate pad of the
SO-DIMM connector and the parallel termination resistor. If the layout requires additional routing
before the termination resistor, return to the same internal layer and transition back out to an external
layer immediately prior to parallel termination resistor.
External trace lengths should be minimized. Intel suggests that the parallel termination be placed on both
sides of the board to simplify routing and minimize trace lengths. All internal and external signals
should be ground reference to keep the path of return current continuous. Intel suggests that all control
signals be routed on the same internal layer.
Resistor packs are acceptable for the parallel (Rt) control termination resistors, but control signals can
not be placed within the same R pack as the data or command signals. The table and diagrams below
depict the recommended topology and layout routing guidelines for the DDR-SDRAM control signals.
134
Relative To SO-DIMM Pin
SO-DIMM0 121
SO-DIMM0 122
SO-DIMM1 121
SO-DIMM1 122
SO-DIMM0 96
SO-DIMM0 95
SO-DIMM1 96
SO-DIMM1 95
®
Intel 855PM Chipset Platform Design Guide
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