Intel 80C186EA Manuals

Manuals and User Guides for Intel 80C186EA. We have 2 Intel 80C186EA manuals available for free PDF download: User Manual, Preliminary Information

Intel 80C186EA User Manual

Intel 80C186EA User Manual (417 pages)

Brand: Intel | Category: Computer Hardware | Size: 2.66 MB

Table of Contents

Table of Contents
4
Chapter 1 Introduction

23
- How to Use this Manual
  23
- Related Documents
  24
- Electronic Support Systems
  25
- Technical Support
  27
- Product Literature
  27
Chapter 2 Overview of the 80C186 Family Architecture

28
- Architectural Overview
  30
  - Execution Unit
    31
  - Bus Interface Unit
    32
  - General Registers
    33
  - Segment Registers
    34
  - Instruction Pointer
    35
  - Flags
    36
  - Memory Segmentation
    37
  - Processor Status Word
    38
  - Logical Addresses
    39
  - Dynamically Relocatable Code
    42
  - 2.1.10 Stack Implementation
    44
  - 2.1.11 Reserved Memory and I/O Space
    44
- Software Overview
  46
  - Instruction Set
    46
    
    Data Transfer Instructions
    47
    
    Arithmetic Instructions
    48
    
    Bit Manipulation Instructions
    50
    
    String Instructions
    51
    
    Program Transfer Instructions
    52
    
    Processor Control Instructions
    56
  - Addressing Modes
    56
    
    Register and Immediate Operand Addressing Modes
    56
    
    Memory Addressing Modes
    57
    
    I/O Port Addressing
    65
    
    Data Types Used in the 80C186 Modular Core Family
    66
    
    Interrupts and Exception Handling
    68
    
    Non-Maskable Interrupts
    71
    
    Maskable Interrupts
    72
    
    Software Interrupts
    74
    
    Interrupt Response Time
    75
    
    Address and Data Bus Concepts
    82
    
    Bit Data Bus
    86
    
    Memory and I/O Interfaces
    87
    
    Bit Bus Memory and I/O Requirements
    88
    
    Address/Status Phase
    91
    
    Data Phase
    94
    
    Idle States
    99
    
    Bus Cycles
    101
    
    Refresh Bus Cycles
    103
    
    Interrupt Acknowledge Bus Cycle
    106
    
    System Design Considerations
    108
    
    HALT Bus Cycle
    109
    
    Temporarily Exiting the HALT Bus State
    112
    
    Exiting HALT
    114
    
    System Design Alternatives
    116
    
    Buffering the Data Bus
    117
    
    Synchronizing Software and Hardware Events
    119
    
    Using a Locked Bus
    120
    
    Using the Queue Status Signals
    121
    
    Multi-Master Bus System Designs
    122
    
    HOLD Bus Latency
    123
    
    Refresh Operation During a Bus HOLD
    124
    
    Exiting HOLD
    126
    
    Bus Cycle Priorities
    127
    
    Peripheral Control Registers
    132
    
    Reserved Locations
    135
    
    F-Bus Operation
    136
    
    Writing the PCB Relocation Register
    137
    
    Considerations for the 80C187 Math Coprocessor Interface
    138
    
    Crystal Oscillator
    142
    
    Oscillator Operation
    143
    
    Selecting Crystals
    146
    
    Using an External Oscillator
    147
    
    Power Management
    151
    
    Idle Mode
    152
    
    Bus Operation During Idle Mode
    154
    
    Leaving Idle Mode
    155
    
    Example Idle Mode Initialization Code
    156
    
    Powerdown Mode
    157
    
    Entering Powerdown Mode
    158
    
    Leaving Powerdown Mode
    159
    
    Power-Save Mode
    160
    
    Leaving Power-Save Mode
    162
    
    Implementing a Power Management Scheme
    164
    
    Common Methods for Generating Chip-Selects
    168
    
    Chip-Select Unit Functional Overview
    169
    
    Programming
    173
    
    Programming the Active Ranges
    179
    
    LCS Active Range
    180
    
    PCS Active Range
    182
    
    Overlapping Chip-Selects
    183
    
    Memory or I/O Bus Cycle Decoding
    184
    
    Chip-Selects and Bus Hold
    185
    
    Refresh Control Unit
    192
    
    Refresh Control Unit 7.1 the Role of the Refresh Control Unit
    193
    
    Refresh Addresses
    195
    
    Refresh Bus Cycles
    196
    
    Programming the Refresh Control Unit
    198
    
    Refresh Base Address Register
    199
    
    Refresh Control Register
    200
    
    Programming Example
    201
    
    Refresh Operation and Bus Hold
    203
    
    Functional Overview
    208
    
    Master Mode
    209
    
    Interrupt Masking
    210
    
    Interrupt Nesting
    211
    
    Functional Operation in Master Mode
    212
    
    Priority Resolution Example
    213
    
    Interrupts that Share a Single Source
    214
    
    Special Fully Nested Mode
    215
    
    Interrupt Acknowledge Sequence
    216
    
    Edge and Level Triggering
    217
    
    Programming the Interrupt Control Unit
    218
    
    Interrupt Control Registers
    219
    
    Interrupt Request Register
    223
    
    Priority Mask Register
    224
    
    In-Service Register
    225
    
    Poll and Poll Status Registers
    226
    
    End-Of-Interrupt (EOI) Register
    228
    
    Interrupt Status Register
    229
    
    Slave Mode
    230
    
    Slave Mode Programming
    232
    
    Interrupt Vector Register
    233
    
    End-Of-Interrupt Register
    234
    
    Other Registers
    235
    
    Interrupt Vectoring in Slave Mode
    236
    
    Initializing the Interrupt Control Unit for Master Mode
    237
    
    Programming the Timer/Counter Unit
    247
    
    Timer 2 Control Register
    250
    
    Initialization Sequence
    252
    
    Clock Sources
    253
    
    Retriggering
    254
    
    Pulsed and Variable Duty Cycle Output
    255
    
    Enabling/Disabling Counters
    256
    
    Timer Interrupts
    257
    
    Synchronization and Maximum Frequency
    258
    
    The DMA Transfer
    268
    
    DMA Transfer Directions
    270
    
    External Requests
    271
    
    Source Synchronization
    272
    
    Internal Requests
    273
    
    DMA Transfer Counts
    274
    
    DMA Unit Interrupts
    275
    
    Programming the Dma Unit
    277
    
    Selecting Byte or Word Size Transfers
    281
    
    Dma Control Register
    282
    
    Selecting the Source of DMA Requests
    284
    
    Arming the DMA Channel
    285
    
    Generating Interrupts on Terminal Count
    286
    
    Suspension of DMA Transfers
    287
    
    DMA Latency
    288
    
    Generating a DMA Acknowledge
    289
    
    Availability of Math Coprocessing
    298
    
    The 80C187 Math Coprocessor
    299
    
    Data Transfer Instructions
    300
    
    Comparison Instructions
    302
    
    Constant Instructions
    303
    
    C187 Data Types
    304
    
    Clocking the 80C187
    307
    
    System Design Tips
    308
    
    Exception Trapping
    310

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Intel 80C186EA Preliminary Information

Intel 80C186EA Preliminary Information (50 pages)

16-Bit High-Integration Embedded Processors

Brand: Intel | Category: Computer Hardware | Size: 0.63 MB

Table of Contents

Table of Contents
2
Introduction

4
80C186Ea Core Architecture

4
- Bus Interface Unit
  4
- Clock Generator
  4
80C186Ea Peripheral Architecture

5
- Interrupt Control Unit
  5
- Timer Counter Unit
  5
- DMA Control Unit
  7
- Chip-Select Unit
  7
- Refresh Control Unit
  7
- Power Management
  7
- 80C187 Interface (80C186EA Only)
  8
- ONCE Test Mode
  8
Differences between the 80C186Xl and the 80C186Ea

8
- Pinout Compatibility
  8
- Operating Modes
  8
- TTL Vs CMOS Inputs
  8
- Timing Specifications
  8
Package Information

9
- Prefix Identification
  9
- Pin Descriptions
  9
- AC Characteristics 80C186EA20
  13
- 80C186EA Pinout
  15
Package Thermal Specifications

20
Electrical Specifications

21
- Absolute Maximum Ratings
  21
- Recommended Connections
  21
DC Specifications

22
- ICC Versus Frequency and Voltage
  24
- PDTMR Pin Delay Calculation
  24
Ac Specifications

25
- AC Characteristics 80L186EA13
  27
- Relative Timings
  29
Ac Test Conditions

30
Ac Timing Waveforms

30
Derating Curves

33
Reset

33
Bus Cycle Waveforms

36
Execution Timings

43
Instruction Set Summary

44
Revision History

50
Errata

50

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