Bit Variable Latency I/O Write Timing (Burst-Of-Four, Variable Wait Cycles Per Beat) - Intel PXA255 Developer's Manual

Figure 6-22. 32-Bit Variable Latency I/O Write Timing (Burst-of-Four, Variable Wait Cycles Per
Beat)
MEMCLK
nCS[0]
MA[25:2]
MA[1:0]
nPWE
nOE
RDnWR
RDY
MD[31:0]
DQM[3:0]
nCS[1]
In Figure 6-21
•
tAS = Address setup to nCS = 1 MEMCLK
•
tCES = nCS setup to nOE or nPWE = 2 MEMCLKs
•
tASRW0 = Address setup to nOE or nPWE low (asserted) = 3 MEMCLKs
•
tASRWn = Address setup to nOE or nPWE low (asserted) = RDN MEMCLKs
•
tDSWH,min = Minimum write data, DQM setup to nPWE high (deasserted) = (RDF+2)
MEMCLKs
•
tDHW = Data, DQM hold after nPWE high (deasserted) = 1 MEMCLK
•
tDHR = Data hold required after nOE deasserted = 0 ns
•
tCEH = nCS held asserted after nOE or nPWE deasserted = 1 MEMCLK
•
tAH = Address hold after nOE or nPWE deasserted = 1 MEMCLK
•
nOE or nPWE high time between burst beats = (RDN+2) MEMCLKs
Intel® PXA255 Processor Developer's Manual
tAS
0
byte addr byte addr
tASRW0
tAH
tCES
RDN+ RDN+2
tDH
tDSWH
D0
mask0
and Figure 6-22, some of the parameters are defined as follows:
1 2
byte addr
tASWN
RDF+1+Waits RDF+1+Waits
D1 D2
mask1 mask2
Memory Controller
3
byte addr
tCEH
RRR*2+1
D3
mask3
6-57