Sign In
Upload
Manuals
Brands
Intel Manuals
Computer Hardware
80331
Intel 80331 Manuals
Manuals and User Guides for Intel 80331. We have
1
Intel 80331 manual available for free PDF download: Design Manual
Intel 80331 Design Manual (148 pages)
I/O Processor
Brand:
Intel
| Category:
Computer Hardware
| Size: 2.06 MB
Table of Contents
Table of Contents
3
Revision History
10
Introduction
11
About this Document
11
Terminology and Definitions
12
Other Relevant Documents
14
About the Intel ® 80331 I/O Processor
15
Package Information
17
FC-Style, H-PBGA Package Dimensions
17
Intel ® 80331 I/O Processor 829-Ball FCBGA Package Diagram
18
Intel ® 80331 I/O Processor Preliminary Ballout (Bottom View)
20
Power Plane Layout
21
Intel ® 80331 I/O Processor Applications
22
Intel ® 80331 I/O Processor PCI-X Adapter Card Block Diagram
22
Terminations
23
Terminations: Pull-Up/Pull-Down
23
Analog Filters
27
VCCPLL Pin Requirements
27
DDR Resistor Compensation
28
Intel 80331 I/O Processor DDRRES Resistor Compensation Circuitry
28
DDR Driver Compensation
29
DDR Driver Compensation Circuitry
29
Routing Guidelines
31
General Routing Guidelines
31
Crosstalk
32
Crosstalk Effects on Trace Distance and Height
32
PCB Ground Layout Around Connectors
33
EMI Considerations
34
Power Distribution and Decoupling
34
Decoupling
34
Decoupling Recommendations
34
Trace Impedance
36
Board Layout Guidelines
37
Motherboard Stack up Information
37
Motherboard Stack Up, Stripline and Microstrip
37
Motherboard Stackup Recommendations
38
Adapter Card Stackup
39
Adapter Card Stack Up, Microstrip and Stripline
39
Adapter Card Stackup
40
PCI-X Layout Guidelines
41
Interrupt Routing and IDSEL Lines
41
Interrupt and IDSEL Mapping
41
PCI Arbitration
42
PCI Resistor Compensation
42
Pci Rcomp
42
PCI General Layout Guidelines
43
PCI-X Topology Layout Guidelines
43
PCI-X Slot Guidelines
43
Intel ® 80331 I/O Processor PCI/X Layout Analysis
44
PCI Clock Layout Guidelines
45
PCI Clock Distribution and Matching Requirements
45
PCI-X Clock Layout Requirements Summary
46
Single-Slot at 133 Mhz
48
Single-Slot Point-To-Point Topology
48
PCI-X 133 Mhz Single Slot Routing Recommendations
48
Embedded PCI-X 133 Mhz
49
Embedded PCI-X 133 Mhz Topology
49
Embedded PCI-X 133 Mhz Routing Recommendations
49
Embedded PCI-X 133 Mhz Alternate Topology
50
Embedded PCI-X 133 Mhz Alternate Topology Routing Recommendations
50
Combination of PCI-X 133 Mhz Slot and Embedded Topology
51
Embedded PCI-X 133 Mhz Topology
51
Embedded and Slot PCI-X 133 Mhz Routing Recommendations
51
Combination PCI-X 133 Mhz Slot and Embedded Topology 2
52
Embedded PCI-X 133 Mhz Topology
52
PCI-X 100 Mhz Slot Topology
53
Slot PCI-X 100 Mhz Slot Routing Topology
53
PCI-X 100 Mhz Slot Topology Routing Recommendations
53
PCI-X 100 Mhz Embedded Topology
54
Embedded PCI-X 100 Mhz Routing Topology
54
PCI-X 100 Mhz Embedded Routing Recommendations
54
PCI-X 100 Mhz Slot and Embedded Topology
55
Combination of Slot and Embedded PCI-X 100 Mhz Routing Topology
55
Combination of Slot and Embedded PCI-X 100 Mhz Routing Recommendations
55
PCI-X 100 Mhz Slot and Embedded Topology 2
56
Combination of Slots and Embedded PCI-X 100 Mhz Routing Topology
56
Combination of Slot and Embedded PCI-X 100 Mhz Routing 2 Recommendations
56
PCI-X 66 Mhz Slot Topology
57
PCI-X 66 Mhz Slot Routing Topology
57
PCI-X 66 Mhz Slot Routing Recommendations
57
PCI-X 66 Mhz Embedded Topology
58
PCI-X 66 Mhz Embedded Routing Topology
58
PCI-X 66 Mhz Embedded Routing Recommendations
58
PCI-X 66 Mhz Mixed Mode Topology
59
PCI-X 66 Mhz Mixed Mode Routing Topology
59
PCI-X 66 Mhz Mixed Mode Routing Recommendations
59
PCI 66 Mhz Slot Topology
60
Contents
60
PCI 66 Mhz Topology
60
PCI 66 Mhz Slot Table
60
PCI 66 Mhz Embedded Table
61
PCI 66 Mhz Embedded Topology
61
PCI 66 Mhz Mixed Mode Topology
62
PCI 66 Mhz Mixed Topology
62
PCI 66 Mhz Mixed Mode Table
62
PCI 33 Mhz Slot Topology
63
PCI 33 Mhz Slot Routing Topology
63
PCI 33 Mhz Slot Routing Recommendations
63
PCI 33 Mhz Embedded Mode Topology
64
PCI 33 Mhz Embedded Mode Routing Topology
64
PCI 33 Mhz Embedded Routing Recommendations
64
PCI 33 Mhz Mixed Topology
65
PCI 33 Mhz Mixed Mode Routing Topology
65
PCI 33 Mhz Mixed Mode Routing Recommendations
65
Memory Controller
67
DDR Bias Voltages
67
DDR II Bias Voltage
67
Intel ® 80331 I/O Processor DDR Overview
68
Core Speed and Memory Configuration
68
DDR 333 Signal Integrity Simulation Conditions
69
Simulated DDR 333 Topologies
69
DDR 333 Stackup Example
70
Example Topologies for DDR Trace
71
Ohm Differential Trace
71
DDR Layout Guidelines
72
Source Synchronous Signal Group
72
X64 DDR Memory Configuration
72
X72 DDR Memory Configuration
72
Routing Requirements
73
Source Synchronous Length Matching
73
Data Group Length Matching
73
Source Synchronous Termination Requirements
73
Source Synchronous Routing Recommendations
74
DIMM DQ/DQS Topology Lengths
75
Die to Ball Internal Lengths
75
DIMM DQ/DQS Topology
79
DIMM DQ/DQS Split Termination Topology
80
DIMM DQ/DQS Split Termination Topology Lengths
80
Clock Signal Groups
81
DIMM Clocked Signal Group Termination
81
Clock Signal Group Registered/Unbuffered DIMM Routing Requirements
82
DDR 333 Registered DIMM Clock Topology
83
Registered DIMM Clock Topology Lengths
83
DDR 333 Unbuffered DIMM Clock Topology
84
Control Signals Termination
85
Trace Length Requirements for Source Clocked Routing
85
Source Clocked Signal Routing
85
Control Signals Routing Guidelines
86
DDR 333 DIMM Unbuffered/Registered Address/CMD Topology Lengths
87
Control Signal DIMM Topology Lengths
88
DDR 333 Embedded Source Synchronous Routing Recommendations
89
DDR 333 Source Synchronous Routine Guidelines
89
Embedded Configuration
89
Embedded DDR 333 DQ/DQS Topology
91
Embedded DDR 333 DQ/DQS Topology Lengths
91
DDR 333 Embedded Clock Routing Recommendations
92
Embedded DDR 333 Buffered Clock Topology
92
DDR 333 Embedded Registered/Unbuffered Clock Routing Recommendations
93
Embedded DDR 333 Buffered Clock Topology Lengths
94
Embedded DDR 333 Unbuffered Clock Topology
95
Embedded DDR 333 Unbuffered Clock Topology Lengths
95
DDR 333 Embedded Address/Command Routing Recommendations
96
DDR 333 Embedded Address/Command/Control Routing Guidelines
96
Embedded DDR 333 Unbuffered ADDR/CMD Topology
98
Embedded DDR 333 Unbuffered Address/CMD Topology Lengths
98
Embedded DDR 333 Registered Address/CMD Topology Lengths
99
Embedded DDR 333 Registered ADDR/CMD Topology
100
DDR II 400 Layout Guidelines
101
X64 DDR Memory Configuration
101
X72 DDR Memory Configuration
101
DDR II Topologies Simulated
102
Simulation Conditions
102
DDRII-400 Trace Width/Impedance Requirements
103
Example Topology for DDRII Trace Width/Impedance Requirements
103
DDR II 400 DIMM Source Synchronous Routing
104
DIMM Layout Design
104
DDRII 400 DIMM Source Synchronous Routing Recommendations
105
DDR II 400 DIMM DQ Lengths
106
DDR II 400 DIMM DQ Topology
106
DDR II 400 DIMM DQS Lengths
106
DDR II 400 DIMM Clock Lengths
107
DDRII 400 Clock Routing Guidelines
107
DDRII 400 DIMM Clock Routing Recommendations
107
DDRII 400 Address/Command/Control Routing Guidelines
108
DDRII 400 DIMM Address/Command/Control Routing Recommendation
108
DDR II 400 DIMM Address/CMD Lengths
109
DDR II 400 DIMM Address/CMD Topology
109
DDRII 400 Embedded Source Synchronous Routine Guidelines
110
DDRII 400 Embedded Source Synchronous Routing Recommendations
110
Embedded Configuration
110
DDR II 400 Embedded DQ Lengths
111
DDR II 400 Embedded DQ Topology
111
DDR II 400 Embedded DQS Lengths
112
DDR II 400 Embedded DQS Topology
112
DDRII 400 Embedded Clock Routing Recommendations
113
DDR II 400 Embedded Clock (PLL) Lengths
114
DDR II 400 Embedded Clock Topology
115
DDRII 400 Embedded Address/Command/Control Routing Guidelines
116
DDRII 400 Embedded Address/Command/Control Routing Recommendations
116
DDR II 400 Embedded Address/CMD Lengths
117
DDR II 400 Embedded Address/Control Topology
118
DDR II 400 Embedded Address/Control Topology with Split Termination
119
DDR Signal Termination
120
DDR Termination Voltage
121
DDR VREF Voltage
121
Peripheral Local Bus
123
Peripheral Bus Signals
123
Address/Data Signal Definitions
123
Control/Status Signal Definitions
123
Bus Width
124
Flash Memory Support
125
Flash Wait State Profile Programming
125
Layout Guidelines for the Peripheral Bus
126
Topology Layout Guidelines
127
Routing Guideline Bidirectional Single Load
127
Routing Guideline Latched Bidirectional Latch Single Load
128
Peripheral Bus Latched Bidirectional Single Load Topology
128
Routing Guideline Latch Bidirectional Two Loads
129
Peripheral Bus Latched Bidirectional Two Load Topology
129
Power Delivery
131
Power Sequencing
131
Intel ® 80331 I/O Processor Bias Voltages
131
Power Failure
132
Theory of Operation
132
Power Failure Sequence
132
Power Delay
133
Battery Backup
134
Non-Battery Backup Circuits
135
Intel ® IQ80331 Evaluation Platform Board
137
Four Peaks Customer Reference Board Features
138
JTAG Circuitry for Debug
139
Requirements
139
JTAG Signals / Header
140
System Requirements
141
JTAG Hardware Requirements
142
Macraigor Raven and Windriver Systems Visionprobe / Visionice
142
ARM Multi-ICE
142
Debug Connectors and Logic Analyzer Connectivity
143
Probing PCI-X Signals
143
Configuration
143
Logic Analyzer Pod 1
143
Logic Analyzer Pod 3
144
Logic Analyzer Pod 2
144
Logic Analyzer Pod 5
145
Logic Analyzer Pod 4
145
Logic Analyzer Pod 6
146
References
147
Related Documents
147
Design References
147
Intel Related Documentation
147
Electronic Information
148
Advertisement
Advertisement
Related Products
Intel 80302
Intel 80303
Intel 80386
Intel 8086-1
Intel 80960HA
Intel 80C186EA
Intel 80L186EA
Intel 80C51FA
Intel 80960SA
Intel 80L186EC
Intel Categories
Motherboard
Computer Hardware
Server
Server Board
Desktop
More Intel Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL