Table 3.8.2 External Bus Pin Functions In Each Mode - Fujitsu F2MC-8L MB89620 Series Hardware Manual

3.8 Memory Access Modes
3.8.2 External Bus Pins
External bus mode must be allowed when connecting external memory or peripheral
functions. In external bus mode, port 0 and port 1 function as the external bus pins
and port 2 functions as the external bus control pins.
n External Bus Pins

Table 3.8.2 External Bus Pin Functions in Each Mode

Pin name
P00/AD0 to
P07/AD7
P10/A08
to P17/A15
P20/BUFC
P21/HAK
P22/HRQ
P23/RDY
P24/CLK
P25/WR
P26/RD
P27/ALE
Check: • In external bus mode, signals are output on the AD0 to AD7, A08 to A15, ALE, and CLK pins
80
CHAPTER 3 CPU
Single-chip mode
Pin
Function
name
Port 0
P00 to General- AD0
P07 purpose to AD7
I/O ports
Port 1
P10 to General- A08 to
P17 purpose A15
I/O ports
P20 BUFC
P21 HAK
P22 HRQ
Port 2
P23 RDY
Output-only
ports
P24 CLK
P25 WR
P26 RD
P27 ALE
even when accessing an internal area. However, the RD, WR, and BUFC pins go to the "H" level.
• The HRQ, HAK, and BUFC pins can be set as output ports by the external bus pin control
register (BCTR).
Memory access mode
External ROM mode or internal ROM/external bus mode
Pin
Function when external bus is operating
name
Address/data multiplex bus I/O
These external bus pins are multiplexed in the time domain to act as
both the output for the lower 8 bits of the address and the data input and
output. The lower address must be latched externally using the ALE
signal.
Address bus output
External bus pins that output the upper 8 bits of the address. Latching is
not required, as the output is maintained when the lower address is
multiplexed with data.
Buffer control output
The signal controls the I/O direction for the external data bus buffer. An
"H" level indicates the output (write) direction and an "L" level indicates
the input (read) direction.
Hold acknowledge output
The signal indicates that the CPU has released the external bus in
response to a hold request input (HRQ) from an external peripheral
function. An "L" level indicates that the external peripheral function can
use the bus.
Hold request input
The signal requests the CPU to release the external bus so that the bus
can be used by an external peripheral function. The external bus pins
and some external bus control pins go to the high-impedance state while
an "H" level is input to this pin.
Ready input
The signal is used to extend the bus cycle when accessing low-speed
external memory or other low-speed external devices. The bus cycle is
extended in the CPU operating clock units while an "L" level is input to
this pin. An external pull-up must be provided for this pin if the ready
function is not used.
Clock output
Outputs the CPU operating clock. The CPU operates in sync with this
clock. This divide-by-two clock (divide-by-four source oscillation) is
called the instruction cycle or the bus cycle.
Write strobe output
Strobe signal for writing data. During a write operation, the pin goes to
the "L" level and the data is output on the data bus. The write destination
reads the data off the data bus on the rising edge of this signal.
Read strobe output
Strobe signal for reading data. During a read operation, the pin goes to
the "L" level and the data is read from the data bus on the rising edge.
Address latch enable output
This signal is used to externally latch the lower address. Connect a latch
that holds the address on the falling edge of this signal.
MB89620 series