5 MOTION DEDICATED PLC INSTRUCTION
(1) This instruction is dedicated instruction toward the Motion CPU in the Multiple
CPU system. Errors occurs when it was executed toward the CPU except the
A part for the number of writing data of the control data specified with (S1) of data
since the device specified with (S2) of the self CPU are stored to since the word
device specified with (D1) of the target CPU (n1) in the Multiple CPU system.
(2) Figure specification of the bit device is possible for (S2) and (D1). However, figure
specification is 4 figures and a start bit device number is only the multiple of 16. It
becomes INSTRCT CODE ERROR  when other values are specified.
(3) If the target CPU is not instruction acceptable condition, even if the S(P).DDWR
instruction is executed, it may not be processed. In this case, it is necessary to
execute the S(P).DDWR instruction again.
S(P).DDWR cannot be executed simultaneously toward the CPU executing
S(P).DDWR instruction.). It can be confirmed by data in the shared CPU memory
of the target CPU (Motion CPU) whether the instruction is acceptable or not.
When the Motion dedicated PLC instruction is started continuously, it is must be
design to execute next instruction after executing instruction complete device on.
(4) The target CPU device range check is not executed with self CPU at the
S(P).DDWR instruction execution, but it checks by the target CPU side, and it
becomes abnormal completion at the device range over.
(5) S(P).DDWR instruction accepting and normal/abnormal completion can be
confirmed with the complete device (D1) or status display device (D2) at the
(a) Complete device
It is turned on by the END processing of scan which the instruction
completed, and turned off by the next END processing.
(b) Status display device at the completion
It is turned on/off according to the status of the instruction completion.
Abnormal completion : It is turned on by the END processing of scan
(6) SM390 turns on when the target CPU specified with (n1) complete to accept.
SM390 turns off when the target CPU specified with (n1) cannot be write correctly
by the reset status or error factor (5000 to 5999).
which the instruction completed, and turned off by
the next END processing.
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