Mitsubishi Electric Q173CPU Programming Manual page 142

3 COMMUNICATION BETWEEN THE PLC CPU AND THE MOTION CPU IN
THE MULTIPLE CPU SYSTEM
Table 3.1 Table of Contents Stored in the Self CPU Operation Data Area
Shared
memory Name
address
Data available/not
0H
available
1H Diagnosis error
2H
Diagnosis-error
3H
occurrence time
4H
5H Error-data category code
6H Error data
7H to 1CH Not used
1DH Switch status
1EH LED status
1FH CPU operation status
Table 3.2 Self CPU Operation Data Area used by the Motion Dedicated PLC Instruction
Shared
memory
address
30H(48) To self CPU high speed interrupt accept flag from CPU1
31H(49) To self CPU high speed interrupt accept flag from CPU2
32H(50) To self CPU high speed interrupt accept flag from CPU3
33H(51) To self CPU high speed interrupt accept flag from CPU4
(1) Self CPU operation data area (0H to 1FFH)
(a) The following data of the self CPU are stored in the Multiple CPU system,
Description
"Data available/not
available" flag
Diagnosis error number
Diagnosis-error
occurrence time
Error-data category code
Error data
—
CPU switch status
CPU-LED status
CPU operation status
(b) The self CPU operation data area is refreshed every time the applicable
register has been changed.
However, the refresh timing may be delayed by up to the main cycle time.
(It updates using idle time during motion control. The maximum main cycle
time: several milliseconds to several hundred milliseconds).
(c) The data of the self CPU operation data area can be read from the PLC
CPU of the other CPU by the FROM instruction.
However, since there is a delay in data update, use the data that has been
read as an object for monitoring only.
(d) Self CPU operation data area used by Motion dedicated PLC instruction
(30H to 33H)
The complete status of the to self CPU high speed interrupt accept flag from
CPUn is stored in the following address.
Name
Detailed explanation
This area is used to check whether data is stored or not in the
self CPU operation data area (1H to 1FH) of the self CPU.
• 0: Data is not stored in the self CPU operation data area.
• 1: Data is stored in the self CPU operation data area.
The error number of an error generated during diagnosis is
stored as a BIN code.
The year and month when the error number was stored in
address 1H of shared CPU memory is stored in 2-digit BCD
code.
The date and hour when the error number was stored in
address 1H of shared CPU memory is stored in 2-digit BCD
code.
The minutes and seconds when the error number was stored in
address 1H of shared CPU memory is stored in 2-digit BCD
code.
Category codes indicating the nature of the stored common
error data and individual error data are stored.
Common data corresponding to the error number of an error
generated during diagnosis is stored.
Not used
The switch status of the CPU is stored.
The bit pattern of the CPU LED is stored
The operation status of the CPU is stored.
(Note) : Refer to the applicable special register for details.
This area is used to check whether to self CPU high speed interrupt accept flag
from CPUn can be accepted or not.
0: To self CPU high speed interrupt accept flag from CPUn accept usable.
1: To self CPU high speed interrupt accept flag from CPUn accept disable.
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Corresponding
(Note)
special resister
D9008
D9010
D9011
D9012
D9013
D9014
D9200
D9201
D9015
Description
—
—