Pll Circuit (Internal System Clock Generating Section) - Epson S1R72104 Technical Manual

6.6 PLL Circuit (Internal System Clock Generating Section)

This IC has the function to generate 40MHz required for the internal circuit from the clock generated by the
oscillation circuit or inputted from EXCK pin by using PLL circuit.
The block diagram around the oscillation section is shown below: Internal clock
EXCLK
OSCIN
5pF
GND
•
The IC allows to structure a oscillation circuit easily by connecting crystal vibrator, ceramic vibrator and
feedback resistance.
(As for the characteristics of the ceramic vibrator, please consult with us separately.)
•
It allows oscillation of 20MHz/22.5MHz/40MHz by means of the oscillation circuit mentioned above.
•
It allows inputting external clock of 5V level and 2.5MHz/20MHz/22.5MHz/40MHz from the EXCLK pin.
•
It allows inputting external clock of 3.3V level and 2.5MHz/20MHz/22.5MHz/40MHz from the OSCIN
pin.
•
No PLL circuit is used because the internal clock can get necessary clock if the oscillator section is
oscillated at 40MHz, or if 40MHz clock is input from EXCLK pin.
•
If EXCLK pin is used, set OSCIN pin to "LOW"; if OSCIN pin is used, set EXCLK pin to "LOW".
Make settings as shown below depending on the ways of use (1:LV
If oscillator circuit is used
Oscillation/
20MHz
input clock
CLKSEL0 0
XPLLPD 1
PLLCNT0 0
PLLCNT1 0
CLKSEL1 0
•
PLL circuit specifications
Lock-up time
Jitter
Rev.1.1
A
B
S
OSCOUT
1MΩ
CLKSEL0
5pF
GND
If external clock of 3.3V level is
22.5MHz 40MHz 2.5MHz
0 0 0
1 0 1
1 0 0
1 0 1
0 1 0
Item
PLL
Y
XPLLPD
PLLCNT0
PLLCNT1
DD
input from OSCIN pin
20MHz 22.5MHz 40MHz
0 0
1 1
0 1
0 1
0 0
Ta=0 to 70°C LV
Specifications
Within 1ms after oscillation was stabilized
Within ±2ns
EPSON
S1R72104 Technical Manual
Internal clock
A
B
S
V
C
CLKSEL1
6.8kΩ
100pF
GND
, 0:V ):
SS
If external clock of 5V level is
input from EXCLK pin
2.5MHz 20MHz
0 1 1
0 1 1
0 0 0
0 1 0
1 0 0
=3.3V±0.3V
DD
Y
22.5MHz 40MHz
1 1
1 0
1 0
1 0
0 1
7