Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3443

Table 53-15: SPI Master Boot BCODE Descriptions (Continued)
BCODE Mode
0x4 FAST READ
0x5 STANDARD
0x6 FAST READ
0x7 RAPID-S
0x8 DOR
0x9 DIOR
0xA QOR READ
(Quad Mode
Method 1)
0xB QIOR READ
(Quad Mode
Method 1)
0xC QOR READ
(Quad Mode
Method 2)
0xD QIOR READ
(Quad Mode
Method 2)
0xE QIOR READ
(Quad Mode
Method 3)
0xF Init
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Command Dummy
Bytes
0x0B 1
0x03 0
0x0B 1
0x1B 2
0x3B 1
0xBB 1
0x6B 1
0xEB 3
0x6B 1
0xEB 3
0xEB 3
Init Init
Data Address SPI Clock
Lines Lines
1 1 SCLK0/2
1 1 SCLK0/3
2 1 SCLK0/1
2 2 SCLK0/1
2 1 SCLK0/2
2 2 SCLK0/2
4 1 SCLK0/2
4 4 SCLK0/2
4 1 SCLK0/2
4 4 SCLK0/2
4 4 SCLK0/2
Init Init Init
Boot Modes
Purpose
Single bit with dummy address
byte. SPI_CTL.FMODE is ena-
bled for full cycle access.
Legacy single bit.
SPI_CTL.FMODE is enabled
for full cycle access.
Single bit with dummy byte.
SPI_CTL.FMODE is enabled
for full cycle access.
Single bit with dummy bytes.
SPI_CTL.FMODE is enabled
for full cycle access.
Dual bit data.
SPI_CTL.FMODE is enabled
for full cycle access.
Dual data and address.
SPI_CTL.FMODE is enabled
for full cycle access.
Quad bit data mode using quad
enable method 1 with
SPI_CTL.FMODE is enabled
for full cycle access.
Quad data and address using
quad enable method 1 with
SPI_CTL.FMODE is enabled
for full cycle access.
Quad data using quad mode ena-
ble method 2.
SPI_CTL.FMODE is enabled
for full cycle access
Quad data and address using
quad mode enable method 2.
SPI_CTL.FMODE is enabled
for full cycle access
Quad data and address using
quad mode enable method 3.
SPI_CTL.FMODE is enabled
for full cycle access
Unused
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