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SSR—Serial Status Register
Receive data register full
Transmit data register empty
0
1
Note: Only 0 can be written, to clear the flag.
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Bit
7
6
TDRE
RDRF
Initial value
1
0
Read/Write
R/(W)
*
R/(W)
Transmit end
0
[Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
1
[Setting conditions]
Reset or transition to standby mode.
TE is cleared to 0 in SCR.
TDRE is 1 when last bit of serial character is transmitted.
Framing error
0
[Clearing conditions]
Reset or transition to standby mode.
Read FER when FER = 1, then write 0
in FER.
1
[Setting condition]
Framing error (stop bit is 0)
0
[Clearing conditions]
Reset or transition to standby mode.
Read RDRF when RDRF = 1, then write 0 in
RDRF.
1
[Setting condition]
Serial data is received normally and transferred
from RSR to RDR
[Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
[Setting conditions]
Reset or transition to standby mode.
TE is 0 in SCR
Data is transferred from TDR to TSR, enabling new
data to be written in TDR.
*
5
4
3
ORER
FER
PER
0
0
0
*
R/(W)
*
R/(W)
*
R/(W)
*
Multiprocessor bit
0
Multiprocessor bit value in
receive data is 0
1
Multiprocessor bit value in
receive data is 1
Parity error
0
[Clearing conditions]
Reset or transition to standby mode.
Read PER when PER = 1, then write 0 in
PER.
1
[Setting condition]
Parity error: (parity of receive data does not
match parity setting of O/
Overrun error
0
[Clearing conditions]
Reset or transition to standby mode.
Read ORER when ORER = 1, then write 0 in
ORER.
1
[Setting condition]
Overrun error (reception of next serial data
ends when RDRF = 1)
514
H'B4
SCI
2
1
0
TEND
MPB
MPBT
1
0
0
R
R
R/W
Multiprocessor bit transfer
0
Multiprocessor bit value in
transmit data is 0
1
Multiprocessor bit value in
transmit data is 1
E
in SMR)
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