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8.1.2 Block Diagrams
ITU Block Diagram (overall): Figure 8-1 is a block diagram of the ITU.
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TCLKA to TCLKD
Clock selector
ø, ø/2, ø/4, ø/8
TOCXA
, TOCXB
4
4
TIOCA
to TIOCA
0
4
TIOCB
to TIOCB
0
4
Legend
TOER:
Timer output master enable register (8 bits)
TOCR:
Timer output control register (8 bits)
TSTR:
Timer start register (8 bits)
TSNC:
Timer synchro register (8 bits)
TMDR:
Timer mode register (8 bits)
TFCR:
Timer function control register (8 bits)
Figure 8-1 ITU Block Diagram (Overall)
Control logic
Counter control and
pulse I/O control unit
Module data bus
172
IMIA0 to IMIA4
IMIB0 to IMIB4
OVI0 to OVI4
TODR
TOCR
TSTR
TSNC
TMDR
TFCR
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