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T
1
t
cyc
t
t
CH
ø
t
CF
t
AD
A
to A
19
0
t
ASD
AS
t
AS1
t
ASD
RD
t
AS1
(read)
t
ACC1
D
to D
7
0
(read)
t
ASD
WR (write)
t
AS1
t
WDD
D
to D
7
0
(write)
Figure 17-4 Basic Bus Cycle: Two-State Access
T
2
CL
t
CR
t
t
t
ACC3
SD
AH
t
t
t
ACC3
SD
AH
t
t
RDS
RDH
t
t
SD
AH
t
WSW1
t
t
WDS1
WDH
439
t
PCH
t
PCH
t
PCH
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