Hitachi H8/3032 Series Hardware Manual page 205

Bit 5—Master Enable TOCXB
Bit 5
EXB4
0
1
Bit 4—Master Enable TOCXA
Bit 4
EXA4
0
1
Bit 3—Master Enable TIOCB
Bit 3
EB3
0
1
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(EXB4): Enables or disables ITU output at pin TOCXB
4
Description
TOCXB output is disabled regardless of TFCR settings (TOCXB
4
input/output pin).
If XTGD = 0, EXB4 is cleared to 0 when input capture A occurs in channel 1.
TOCXB is enabled for output according to TFCR settings
4
(EXA4): Enables or disables ITU output at pin TOCXA
4
Description
TOCXA output is disabled regardless of TFCR settings (TOCXA
4
input/output pin).
If XTGD = 0, EXA4 is cleared to 0 when input capture A occurs in channel 1.
TOCXA is enabled for output according to TFCR settings
4
(EB3): Enables or disables ITU output at pin TIOCB
3
Description
TIOCB output is disabled regardless of TIOR3 and TFCR settings (TIOCB
3
a generic input/output pin).
If XTGD = 0, EB3 is cleared to 0 when input capture A occurs in channel 1.
TIOCB is enabled for output according to TIOR3 and TFCR settings
3
operates as a generic
4
operates as a generic
4
190
.
4
(Initial value)
.
4
(Initial value)
.
3
operates as
3
(Initial value)