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Table 8-11 (d) ITU Operating Modes (Channel 3)
TSNC
TMDR
Synchro-
Operating Mode
nization
MDF
FDIR PWM
Synchronous preset
SYNC3 = 1 —
—
PWM mode
—
—
o
Output compare A
—
—
o
Output compare B
—
—
o
Input capture A
—
—
o
Input capture B
—
—
o
Counter By compare
—
—
o
clearing
match/input
capture A
By compare
—
—
o
match/input
capture B
Syn-
SYNC3 = 1 —
—
chronous
clear
Complementary
*3
—
—
o
PWM mode
Reset-synchronized
—
—
o
PWM mode
Buffering
—
—
o
(BRA)
Buffering
—
—
o
(BRB)
Legend:
Setting available (valid). — Setting does not affect this mode.
o
Notes: 1. Master enable bit settings are valid only during waveform output.
2. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
3. Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected.
4. The counter cannot be cleared by input capture A when reset-synchronized PWM mode is selected.
5. In complementary PWM mode, select the same clock source for channels 3 and 4.
6. Use the input capture A function in channel 1.
Register Settings
TFCR
Comple-
Reset-
mentary
Synchro-
PWM
nized PWM Buffering
XTGD Select Enable
*3
—
o
o
o
o
PWM3 = 1 CMD1 = 0
CMD1 = 0
—
o
PWM3 = 0 CMD1 = 0
CMD1 = 0
—
o
CMD1 = 0
CMD1 = 0
—
o
o
PWM3 = 0 CMD1 = 0
CMD1 = 0
—
o
PWM3 = 0 CMD1 = 0
CMD1 = 0
—
o
Illegal setting:
*4
—
o
o
o
CMD1 = 1
CMD0 = 0
CMD1 = 0
CMD1 = 0
—
o
o
Illegal setting:
—
o
o
o
CMD1 = 1
CMD0 = 0
—
CMD1 = 1
CMD1 = 1
*6
o
o
CMD0 = 0
CMD0 = 0
—
CMD1 = 1
CMD1 = 1
*6
o
o
CMD0 = 1
CMD0 = 1
BFA3 = 1
—
o
o
o
Other bits
unrestricted
BFB3 = 1
—
o
o
o
Other bits
unrestricted
267
TOCR
TOER
TIOR3
Output
Level
Master
Clear
IOA
IOB
Select
—
*1
o
o
o
o
—
—
*2
o
o
o
—
IOA2 = 0
o
o
o
Other bits
unrestricted
—
IOB2 = 0
o
o
o
Other bits
unrestricted
—
EA3 ignored IOA2 = 1
o
o
Other bits
Other bits
unrestricted unrestricted
—
EA3 ignored
IOA2 = 1
o
o
Other bits
Other bits
unrestricted
unrestricted
—
*1
CCLR1 = 0
o
o
o
CCLR0 = 1
—
*1
CCLR1 = 1
o
o
o
CCLR0 = 0
—
*1
CCLR1 = 1
o
o
o
CCLR0 = 1
—
—
CCLR1 = 0
o
o
CCLR0 = 0
—
—
CCLR1 = 0
o
o
CCLR0 = 1
—
*1
o
o
o
o
—
*1
o
o
o
o
TCR3
Clock
Select
o
o
o
o
o
o
o
o
o
*5
o
o
o
o
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