Register Configuration - Hitachi H8/3032 Series Hardware Manual

8.1.4 Register Configuration

Table 8-3 summarizes the ITU registers.
Table 8-3 ITU Registers
Channel
Common
0
1
Notes: 1. The lower 16 bits of the address are indicated.
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Address *1 Name
H'FF60 Timer start register
H'FF61 Timer synchro register
H'FF62 Timer mode register
H'FF63 Timer function control register
H'FF90 Timer output master enable register
H'FF91 Timer output control register
H'FF64 Timer control register 0
H'FF65 Timer I/O control register 0
H'FF66 Timer interrupt enable register 0
H'FF67 Timer status register 0
H'FF68 Timer counter 0 (high)
H'FF69 Timer counter 0 (low)
H'FF6A General register A0 (high)
H'FF6B General register A0 (low)
H'FF6C General register B0 (high)
H'FF6D General register B0 (low)
H'FF6E Timer control register 1
H'FF6F Timer I/O control register 1
H'FF70 Timer interrupt enable register 1
H'FF71 Timer status register 1
H'FF72 Timer counter 1 (high)
H'FF73 Timer counter 1 (low)
H'FF74 General register A1 (high)
H'FF75 General register A1 (low)
H'FF76 General register B1 (high)
H'FF77 General register B1 (low)
2. Only 0 can be written, to clear flags.
Abbre-
viation
TSTR
TSNC
TMDR
TFCR
TOER
TOCR
TCR0
TIOR0
TIER0
TSR0
TCNT0H
TCNT0L
GRA0H
GRA0L
GRB0H
GRB0L
TCR1
TIOR1
TIER1
TSR1
TCNT1H
TCNT1L
GRA1H
GRA1L
GRB1H
GRB1L
178
Initial
R/W Value
R/W H'E0
R/W H'E0
R/W H'80
R/W H'C0
R/W H'FF
R/W H'FF
R/W H'80
R/W H'88
R/W H'F8
*2
R/(W) H'F8
R/W H'00
R/W H'00
R/W H'FF
R/W H'FF
R/W H'FF
R/W H'FF
R/W H'80
R/W H'88
R/W H'F8
*2
R/(W) H'F8
R/W H'00
R/W H'00
R/W H'FF
R/W H'FF
R/W H'FF
R/W H'FF