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The receive margin in asynchronous mode can therefore be expressed as in equation (1).
M = | (0.5 –
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2).
D = 0.5, F = 0
M = [0.5 – 1/(2 × 16)] × 100%
= 46.875%.................................................................................................(2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
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8 clocks
0
Internal
base clock
Receive data
Start bit
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 11-21 Receive Data Sampling Timing in Asynchronous Mode
1
) – (L – 0.5) F –
2N
16 clocks
7
15 0
| D – 0.5 |
×
(1 + F) |
100%
...................(1)
N
368
7
15 0
D
D
0
1
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