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Block Diagram of Channel 2: Figure 8-3 is a block diagram of channel 2. This is the channel
that provides only 0 output and 1 output.
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TCLKA to TCLKD
Clock selector
ø, ø/2, ø/4, ø/8
Legend
TCNT2:
Timer counter 2 (16 bits)
GRA2, GRB2:
General registers A2 and B2 (input capture/output compare registers)
×
(16 bits
2)
TCR2:
Timer control register 2 (8 bits)
TIOR2:
Timer I/O control register 2 (8 bits)
TIER2:
Timer interrupt enable register 2 (8 bits)
TSR2:
Timer status register 2 (8 bits)
Figure 8-3 Block Diagram of Channel 2
Comparator
Control logic
Module data bus
174
TIOCA
2
TIOCB
2
IMIA2
IMIB2
OVI2
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