Hitachi H8/3032 Series Hardware Manual page 291

Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered
by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFA5
and the address of the lower 4 bits (group 0) is H'FFA7. Bits 3 to 0 of address H'FFA5 and bits 7
to 4 of address H'FFA7 are reserved bits that cannot be modified and always read 1.
Address H'FFA5
Bit
Initial value
Read/Write
Address H'FFA7
Bit
Initial value
Read/Write
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7 6 5
NDR7 NDR6 NDR5 NDR4
0 0 0
R/W R/W R/W
Next data 7 to 4
These bits store the next output
data for TPC output group 1
7 6 5
— — —
1 1 1
— — —
Reserved bits
276
4 3 2
— —
0 1 1
R/W — —
Reserved bits
4 3 2
— NDR3 NDR2 NDR1
1 0 0
— R/W R/W R/W
Next data 3 to 0
These bits store the next output
data for TPC output group 0
1 0
— —
1 1
— —
1 0
NDR0
0 0
R/W