Hitachi H8/3032 Series Hardware Manual page 468

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Table A-1 Instruction Set (cont)
Mnemonic Operation
W ERd32 ÷ Rs16 →ERd32
DIVXU. W Rs, ERd
(Ed: remainder,
Rd: quotient)
(unsigned division)
Rd16 ÷ Rs8 → Rd16
DIVXS. B Rs, Rd B
(RdH: remainder,
RdL: quotient)
(signed division)
W ERd32 ÷ Rs16 → ERd32
DIVXS. W Rs, ERd
(Ed: remainder,
Rd: quotient)
(signed division)
CMP.B #xx:8, Rd B Rd8–#xx:8
CMP.B Rs, Rd B Rd8–Rs8
CMP.W #xx:16, Rd W Rd16–#xx:16
CMP.W Rs, Rd W Rd16–Rs16
CMP.L #xx:32, ERd L ERd32–#xx:32
CMP.L ERs, ERd L ERd32–ERs32
0–Rd8 → Rd8
NEG.B Rd B
W 0–Rd16 → Rd16
NEG.W Rd
0–ERd32 → ERd32
NEG.L ERd L
W 0 → (<bits 15 to 8>
EXTU.W Rd
of Rd16)
0 → (<bits 31 to 16>
EXTU.L ERd L
of Rd32)
W (<bit 7> of Rd16) →
EXTS.W Rd
(<bits 15 to 8> of Rd16)
(<bit 15> of Rd32) →
EXTS.L ERd L
(<bits 31 to 16> of
ERd32)
Addressing Mode and
Instruction Length (bytes)
Condition Code
I H N Z
2 — — 6
4 — — 8
4 — — 8
2 —
2 —
4 — 1
2 — 1
6 — 2
2 — 2
2 —
2 —
2 —
2 — — 0
2 — — 0
2 — —
2 — —
453
No. of
*1
States
V C
7 — — 22
7 — — 16
7 — — 24
2
2
4
2
4
2
2
2
2
0 — 2
0 — 2
0 — 2
0 — 2