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8-Bit, Two-State-Access Areas: Figure 6-4 shows the timing of bus control signals for an 8-bit,
two-state-access area. Wait status cannot be inserted.
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Address bus
AS
RD
Read
access
D
to D
7
0
WR
Write
access
D
to D
7
0
Figure 6-4 Bus Control Signal Timing for 8-Bit, Two-State-Access Area
Bus cycle
T
T
1
2
External address
Valid
Valid
110
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