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State: Figure D-2 is a timing diagram for the case in which RES goes low during the
Reset in T
2
state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
T
2
the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The
address bus is initialized to the low output level 0.5 state after the low level of RES is sampled.
The same timing applies when a reset occurs during a wait state (T
ø
RES
Internal
reset signal
Address bus
(mode 1)
AS (mode 1)
RD (read access)
(mode 1)
WR (write access)
(mode 1)
Data bus
(write access)
(mode 1)
I/O port
(modes 1 to 3)
Figure D-2 Reset during Memory Access (Reset during T
).
W
Access to external address
T
T
T
1
2
3
553
H'000000
High impedance
High impedance
State)
2
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