Hitachi H8/3032 Series Hardware Manual page 500

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TMDR—Timer Mode Register
Bit 7
— MDF
Initial value 1
Read/Write — R/W
PWM mode 4
0 Channel 4 operates normally
1 Channel 4 operates in PWM mode
Flag direction
0 OVF is set to 1 in TSR2 when TCNT2 overflows or underflows
1 OVF is set to 1 in TSR2 when TCNT2 overflows
Phase counting mode flag
0 Channel 2 operates normally
1 Channel 2 operates in phase counting mode
6 5 4 3
FDIR PWM4 PWM3
0 0 0 0
R/W R/W R/W
PWM mode 0
0 Channel 0 operates normally
1 Channel 0 operates in PWM mode
PWM mode 1
0 Channel 1 operates normally
1 Channel 1 operates in PWM mode
PWM mode 2
0 Channel 2 operates normally
1 Channel 2 operates in PWM mode
PWM mode 3
0 Channel 3 operates normally
1 Channel 3 operates in PWM mode
485
H'62 ITU (all channels)
2 1 0
PWM2 PWM1 PWM0
0 0 0
R/W R/W R/W