Hitachi H8/3032 Series Hardware Manual page 379

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Initialize
Start transmitting and receiving
Read TDRE flag in SSR
No
TDRE = 1?
Yes
Write transmit data in TDR and
clear TDRE flag to 0 in SSR
Read ORER flag in SSR
ORER = 1?
No
Read RDRF flag in SSR
No
RDRF = 1?
Yes
Read receive data from RDR
and clear RDRF flag to 0 in SSR
No
End of transmitting and
receiving?
Yes
Clear TE and RE bits to 0 in SCR
End
Note: * When switching from transmitting or receiving to simultaneous
transmitting and receiving, clear the TE and RE bits both to 0,
then set the TE and RE bits both to 1.
Figure 11-20 Sample Flowchart for Serial Transmitting
1. SCI initialization: the transmit data
output function of the TxD pin and
1
receive data input function of the
RxD pin are selected, enabling
simultaneous transmitting and
receiving.
2. SCI status check and transmit
data write: read SSR, check that
2
the TDRE flag is 1, then write
transmit data in TDR and clear
the TDRE flag to 0.
Notification that the TDRE flag has
changed from 0 to 1 can also be
given by the TXI interrupt.
3. Receive error handling: if a receive
error occurs, read the ORER flag in
SSR, then after executing the neces-
sary error handling, clear the ORER
flag to 0.
Neither transmitting nor receiving
can resume while the ORER flag
remains set to 1.
4. SCI status check and receive
data read: read SSR, check that
the RDRF flag is 1, then read
Yes
receive data from RDR and clear
the RDRF flag to 0. Notification
3
that the RDRF flag has changed
from 0 to 1 can also be given
Error handling
by the RXI interrupt.
5. To continue transmitting and
4
receiving serial data: check the
RDRF flag, read RDR, and clear
the RDRF flag to 0 before the
MSB (bit 7) of the current frame
is received. Also check that the
TDRE flag is (bit 7) of the current
frame is received. Also check that
the TDRE flag is set to 1, indicat-
ing that data can be written, write
data in TDR, then clear the TDRE
flag to 0 before the MSB (bit 7) of
the current frame is transmitted.
When the DMAC is activated by
a transmit-data-empty interrupt
request (TXI) to write data in TDR,
5
the TDRE flag is checked and
cleared automatically.
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