Hitachi H8/3032 Series Hardware Manual page 543

SYSCR—System Control Register
Downloaded from Elcodis.com electronic components distributor
Bit 7 6
SSBY STS2
Initial value 0 0
Read/Write
R/W R/W
Standby timer select 2 to 0
Bit 6
STS2
0
1
Software standby
0 SLEEP instruction causes transition to sleep mode
1 SLEEP instruction causes transition to software standby mode
H'F2
5 4 3
STS1 STS0 UE
0 0 1
R/W R/W R/W
NMI edge select
0 An interrupt is requested at the falling edge of NMI
1 An interrupt is requested at the rising edge of NMI
User bit enable
0 CCR bit 6 (UI) is used as an interrupt mask bit
1 CCR bit 6 (UI) is used as a user bit
Bit 5 Bit 4
STS1 STS0 Standby Timer
0 0 Waiting time = 8192 states
1 Waiting time = 16384 states
1 0 Waiting time = 32768 states
1 Waiting time = 65536 states
0 — Waiting time = 131072 states
1 — Illegal setting
528
System control
2 1 0
NMIEG — RAME
0 1 1
R/W — R/W
RAM enable
0 On-chip RAM is disabled
1 On-chip RAM is enabled