Hitachi H8/3032 Series Hardware Manual page 306

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Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non-
Overlapping Output): Figure 9-7 shows an example of the use of TPC output for four-phase
complementary non-overlapping pulse output.
TCNT value
GRB
TCNT
GRA
H'0000
NDRB
95
65
PBDR
00
95
TP
15
TP
14
TP
13
TP
12
TP
11
TP
10
TP
9
TP
8
The ITU channel to be used as the output trigger channel is set up so that GRA and GRB are output
compare registers and the counter will be cleared by compare match B. The TPC output trigger
period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TIER to enable
IMFA interrupts.
H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set
Bits G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is
written in NDRB.
The timer counter in this ITU channel is started. When compare match B occurs, outputs change from
1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed
by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRB.
Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95...
at successive IMFA interrupts.
Figure 9-7 Non-Overlapping TPC Output Example (Four-Phase Complementary
59
56
95
05
65
41
59
50
56
14
Non-overlap margin
Non-Overlapping Pulse Output)
291
Time
65
95
05
65

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