Hitachi H8/3032 Series Hardware Manual page 274

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Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T state of a general register read cycle, the value before input capture is read.
3
See figure 8-66.
ø
Address
Internal read signal
Input capture signal
GR
Internal data bus
Figure 8-66 Contention between General Register Read and Input Capture
General register read cycle
T T T
1 2 3
GR address
X M
X
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